Oscillator, method of operating the same, and PWM controller including the same

1. An oscillator for a pulse width modulation (PWM) controller, comprising:

an oscillation circuit including a capacitor and configured to generate a first pulse signal by charging and discharging the capacitor;

a frequency divider configured to generate a second pulse signal based on the first pulse signal, the second pulse signal having a lower frequency than the first pulse signal; and

an oscillation control circuit coupled to the oscillation circuit and the frequency divider and configured to generate control signals for holding the charging and discharging of the capacitor during an oscillation holding operation,

wherein the PWM controller utilizes a boundary conduction mode (BCM) control algorithm, and

wherein the oscillation control circuit generates the control signals based on the first pulse signal, a BCM end detection signal, and a pulse detection signal.

2. The oscillator of claim 1 , wherein the BCM end detection signal is enabled when an output voltage of a device including the PWM controller is turned on and disabled when a storage energy of a load coupled to the device is zero.

3. The oscillator of claim 1 , wherein the oscillation holding operation is activated when the BCM end detection signal and the pulse detection signal are enabled, and deactivated when the BCM end detection signal is disabled,

wherein the frequency divider generates the pulse detection signal by detecting an (N−j)th cycle of the first pulse signal among N cycles of the first pulse signal that correspond to one cycle of the second pulse signal, and

wherein N and j are positive integers, the N being greater than j.

4. The oscillator of claim 1 , wherein the oscillation control circuit comprises:

a state machine that receives the BCM end detection signal, the pulse detection signal, and the first pulse signal, as input signals, and generates the control signals and an intermediate pulse signal based on the input signals, the intermediate pulse signal corresponding to the first pulse signal and being input to the frequency divider.

5. The oscillator of claim 1 , wherein the oscillation holding operation is activated when the BCM end detection signal and the pulse detection signal are enabled, and deactivated when the BCM end detection signal is disabled,

wherein the frequency divider generates the pulse detection signal by detecting an (N−j)th cycle of the first pulse signal among N cycles of the first pulse signal that correspond to one cycle of the second pulse signal,

wherein N and j are positive integers, the N being greater than j, and

wherein the pulse detection signal is enabled at a rising edge or a falling edge of the (N−j)th cycle of the first pulse signal.

6. The oscillator of claim 1 , wherein the oscillation circuit comprises:

a triangular pulse generating circuit configured to perform a charging or discharging operation of the capacitor in response to the control signals from the oscillation control circuit, and generate a triangular pulse signal;

a first comparator configured to receive the triangular pulse signal at a positive input terminal, and receive a first reference voltage at a negative input terminal;

a second comparator configured to receive a second reference voltage at a positive input terminal, and receive the triangular pulse signal at a negative input terminal; and

a RS flip-flop configured to receive an output signal of the first comparator at a set input terminal, receive an output signal of the second comparator at a reset input terminal, and output the first pulse signal,

wherein the first reference voltage and the second reference voltage determine a swing width of the triangular pulse signal.

7. The oscillator of claim 6 , wherein the triangular pulse generating circuit comprises:

the capacitor;

a first switch coupled to the capacitor and configured to charge the capacitor with a sourcing current in response to a first one of the control signals; and

a second switch coupled to capacitor and configured to discharge the capacitor with a sinking current in response to a second one of the control signals,

wherein the oscillation control circuit generates the first and second control signals to turn off the first and second switches during the oscillation holding operation.

8. The oscillator of claim 1 ,

wherein the frequency of the second pulse signal is within a target frequency range of the oscillator,

wherein the oscillation holding operation is activated when the BCM end detection signal and the pulse detection signal are enabled, and deactivated when the BCM end detection signal is disabled,

wherein the frequency divider generates the pulse detection signal by detecting an (N−j)th cycle of the first pulse signal among N cycles of the first pulse signal that correspond to one cycle of the second pulse signal,

wherein N and j are positive integers, the N being greater than j, and

wherein the N is determined by a minimum frequency in the target frequency range.

9. The oscillator of claim 8 , wherein the j increases as the N increases.

10. The oscillator of claim 9 , wherein the N is within a range of 8 to 20.

11. A method of operating an oscillator for a pulse width modulation (PWM) controller, the method comprising:

generating a first pulse signal by charging and discharging a capacitor in response to control signals in order to perform an oscillation operation;

generating a second pulse signal based on the first pulse signal, the second pulse signal having a lower frequency than the first pulse signal;

holding the oscillation operation by generating the control signals in order to deactivate the charging and discharging of the capacitor of the oscillator; and

resuming the oscillation operation by generating the control signals for activating one of the charging and discharging operations of the capacitor

wherein the PWM controller utilizes a boundary conduction mode (BCM) control algorithm, and

wherein the control signals are generated based on the first pulse signal, a BCM end detection signal, and a pulse detection signal.

12. The method of claim 11 ,

wherein the BCM end detection signal is enabled when an output voltage of a device including the PWM controller is turned on and disabled when a storage energy of a load coupled to the device is zero.

13. The method of claim 12 , wherein the oscillation operation is held when the BCM end detection signal and the pulse detection signal are enabled, and

wherein the oscillation operation is resumed when the BCM end detection signal is disabled,

wherein the pulse detection signal is generated by a frequency divider of the oscillator by detecting an (N−j)th cycle of the first pulse signal among N cycles of the first pulse signal that correspond to one cycle of the second pulse signal, and

wherein N and j are positive integers, the N being greater than j.

14. A pulse width modulation (PWM) controller that utilizes a boundary conduction mode (BCM) control algorithm, comprising:

a logic part configured to generate a BCM end detection signal; and

an oscillator configured to perform an oscillation operation to generate a first pulse signal having a first frequency, perform a 1/N frequency dividing operation based on the first pulse signal to generate a second pulse signal having a second frequency that varies in a target frequency range of the oscillator, and perform an oscillation holding operation for holding the oscillation operation based on the BCM end detection signal and an (N−j)th pulse detection signal, j being a positive integer smaller than N,

wherein the first frequency is N times higher than the second frequency, and

wherein the oscillator generates the (N−j)th pulse detection signal by detecting an (N−j)th cycle of the first pulse signal among N cycles of the first pulse signal that correspond to one cycle of the second pulse signal.

15. The PWM controller of claim 14 , wherein the BCM end detection signal is enabled when an output voltage of a device including the PWM controller is turned on and disabled when a storage energy of a load coupled to the device is zero.

16. The PWM controller of claim 14 , wherein the oscillation holding operation is activated when both of the BCM end detection signal and the (N−j)th pulse detection signal are enabled, and deactivated when the BCM end detection signal is disabled.

17. The PWM controller of claim 14 , wherein the oscillator comprises:

an oscillation circuit including a capacitor and configured to generate the first pulse signal by charging and discharging the capacitor using a sourcing current and a sinking current, the first frequency of the first pulse signal corresponding to a charging or discharging speed of the capacitor;

a 1/N frequency divider configured to perform the 1/N frequency dividing operation to generate the second pulse signal; and

an oscillation control circuit coupled between the oscillation circuit and the 1/N frequency divider and configured to control the oscillation operation and the oscillation holding operation by controlling the charging and discharging operations of the capacitor based on the first pulse signal, the BCM end detection signal, and the (N−j)th pulse detection signal,

wherein the 1/N frequency divider further generates the (N−j)th pulse detection signal.

18. The PWM controller of claim 17 , wherein the oscillation control circuit comprises:

a state machine that receives the BCM end detection signal, the (N−j)th pulse detection signal, and the first pulse signal, as input signals, and generates the control signals and an intermediate pulse signal based on the input signals, the intermediate pulse signal corresponding to the first pulse signal and being input to the 1/N frequency divider.

19. The PWM controller of claim 17 , wherein the oscillation control circuit comprises:

a NAND gate receiving the BCM end detection signal and the (N−j)th pulse detection signal;

an AND gate receiving the first pulse signal and an output signal of the NAND gate, and generating a second one of the control signals; and

an OR gate receiving the first pulse signal and an inverted signal of the output signal of the NAND gate and generating a first one of the control signals,

wherein the first control signal corresponds to an intermediate pulse signal that is input to the 1/N frequency divider.