Semiconductor memory device

1. A semiconductor memory device, comprising:

a free magnetic pattern on a substrate;

a reference magnetic pattern on the free magnetic pattern, the reference magnetic pattern including a first pinned pattern, a second pinned pattern, and an exchange coupling pattern between the first and second pinned patterns;

a tunnel barrier pattern between the reference magnetic pattern and the free magnetic pattern;

a polarization enhancement magnetic pattern between the tunnel barrier pattern and the first pinned pattern; and

an intervening pattern between the polarization enhancement magnetic pattern and the first pinned pattern,

wherein the first pinned pattern includes first ferromagnetic patterns and first non-magnetic patterns which are alternately stacked, the first ferromagnetic patterns including cobalt (Co) and the first non-magnetic patterns including iridium (Ir), and

wherein the second pinned pattern includes CoPt or CoPt alloy.

2. The semiconductor memory device as claimed in claim 1 , wherein:

the first pinned pattern includes an odd number of the first ferromagnetic patterns and an even number of the first non-magnetic patterns, and

a thickness of one even-numbered first ferromagnetic pattern of the first ferromagnetic patterns is greater than a thickness of one odd-numbered first ferromagnetic pattern of the first ferromagnetic patterns.

3. The semiconductor memory device as claimed in claim 1 , wherein:

the first pinned pattern includes an even number of the first ferromagnetic patterns and an even number of the first non-magnetic patterns, and

a thickness of one odd-numbered first ferromagnetic pattern of the first ferromagnetic patterns is substantially equal to a thickness of one even-numbered first ferromagnetic pattern of the first ferromagnetic patterns.

4. The semiconductor memory device as claimed in claim 1 , wherein the free magnetic pattern and the polarization enhancement magnetic pattern are in contact with the tunnel barrier pattern.

5. The semiconductor memory device as claimed in claim 1 , wherein the first pinned pattern has a different crystal structure from the polarization enhancement magnetic pattern.

6. The semiconductor memory device as claimed in claim 1 , wherein the polarization enhancement magnetic pattern has a same crystal structure as the free magnetic pattern.

7. The semiconductor memory device as claimed in claim 1 , wherein the polarization enhancement magnetic pattern includes a magnetic material with a magnetic moment having a magnitude that is greater than a magnitude of a magnetic moment of the first pinned pattern.

8. The semiconductor memory device as claimed in claim 1 , wherein each of the first non-magnetic patterns includes a non-magnetic material that couples first ferromagnetic patterns adjacent to each other to have magnetic moments of the adjacent first ferromagnetic patterns anti-parallel to each other.

9. The semiconductor memory device as claimed in claim 1 , wherein the intervening pattern includes a non-magnetic material that is in contact with the polarization enhancement magnetic pattern and one of the first ferromagnetic patterns of the first pinned pattern to couple the polarization enhancement magnetic pattern and the one first ferromagnetic pattern in such a way that a magnetic moment of the polarization enhancement magnetic pattern is parallel to a magnetic moment of the one first ferromagnetic pattern.

10. A semiconductor memory device, comprising:

a free magnetic pattern on a substrate;

a reference magnetic pattern on the free magnetic pattern, the reference magnetic pattern including a first pinned pattern, a second pinned pattern, and an exchange coupling pattern between the first and second pinned patterns;

a tunnel barrier pattern between the reference magnetic pattern and the free magnetic pattern;

a polarization enhancement magnetic pattern between the tunnel barrier pattern and the first pinned pattern; and

an intervening pattern between the polarization enhancement magnetic pattern and the first pinned pattern,

wherein the first pinned pattern includes first ferromagnetic patterns and first non-magnetic patterns which are alternately stacked, the first ferromagnetic patterns including cobalt (Co), and the first non-magnetic patterns including iridium (Ir), and

wherein the second pinned pattern includes a first element that is a same ferromagnetic material as in the first ferromagnetic patterns, and includes a second element that is a different non-magnetic material from the first non-magnetic patterns.

11. The semiconductor memory device as claimed in claim 10 , wherein:

the first pinned pattern includes an odd number of the first ferromagnetic patterns and an even number of the first non-magnetic patterns, and

a thickness of one even-numbered first ferromagnetic pattern of the first ferromagnetic patterns is greater than a thickness of one odd-numbered first ferromagnetic pattern of the first ferromagnetic patterns.

12. The semiconductor memory device as claimed in claim 10 , wherein:

the first pinned pattern includes an even number of the first ferromagnetic patterns and an even number of the first non-magnetic patterns, and

a thickness of one odd-numbered first ferromagnetic pattern of the first ferromagnetic patterns is substantially equal to a thickness of one even-numbered first ferromagnetic pattern of the first ferromagnetic patterns.

13. The semiconductor memory device as claimed in claim 10 , wherein thicknesses of the first ferromagnetic patterns of the first pinned pattern are substantially equal to each other.

14. The semiconductor memory device as claimed in claim 10 , wherein the free magnetic pattern and the polarization enhancement magnetic pattern are in contact with the tunnel barrier pattern.

15. The semiconductor memory device as claimed in claim 10 , wherein the first pinned pattern has a different crystal structure from the polarization enhancement magnetic pattern.

16. The semiconductor memory device as claimed in claim 10 , wherein the polarization enhancement magnetic pattern has the same crystal structure as the free magnetic pattern.

17. The semiconductor memory device as claimed in claim 10 , wherein the polarization enhancement magnetic pattern includes a magnetic material with a magnetic moment having a magnitude that is greater than a magnitude of a magnetic moment of the first pinned pattern.

18. The semiconductor memory device as claimed in claim 10 , wherein the second pinned pattern includes a CoPt alloy.

19. A semiconductor memory device, comprising:

a free magnetic pattern on a substrate;

a reference magnetic pattern on the free magnetic pattern, the reference magnetic pattern including a first pinned pattern, a second pinned pattern, and an exchange coupling pattern between the first and second pinned patterns;

a tunnel barrier pattern between the reference magnetic pattern and the free magnetic pattern;

a polarization enhancement magnetic pattern between the tunnel barrier pattern and the first pinned pattern; and

an intervening pattern between the polarization enhancement magnetic pattern and the first pinned pattern,

wherein the first pinned pattern includes first ferromagnetic patterns and first non-magnetic patterns which are alternately stacked,

wherein each of the first non-magnetic patterns includes a non-magnetic material that couples first ferromagnetic patterns adjacent to each other to have magnetic moments of the adjacent first ferromagnetic patterns anti-parallel to each other, and

wherein the second pinned pattern includes CoPt or CoPt alloy.