IP Library Granted Patent US 10,198,191
Granted Patent B2
US 10,198,191 · App. 15/816,767 · Granted Feb 5, 2019

Memory card and host device thereof

Inventor: Takafumi Ito (Ome, JP)
Assignee: TOSHIBA MEMORY CORPORATION
G06F3/0611G06F3/0659G06F3/0679G06F12/1433G06F13/4234G11C7/22G06F2003/0692G06F2206/1014
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,198,191
App. No.
15/816,767
Granted
Feb 5, 2019
Kind
B2
Abstract

A memory card is attached to a host device, and includes a data control circuit which transfers data with respect to the host device in synchronism with a rise edge and a fall edge of a clock signal.

Claims (97)

1. A storage device comprising:

a command terminal;

a plurality of data terminals;

a clock terminal;

a power terminal for a power supply voltage;

a ground terminal for a ground voltage;

a nonvolatile memory; and

a controller coupled to the command terminal, the data terminals, the clock terminal, the power terminal, and the ground terminal,

wherein the controller is configured to receive the clock signal through the clock terminal from the outside of the storage device,

wherein the controller is configured to output a first status data through at least one of the data terminals to the outside of the storage device, in accordance with only one of a rising edge and a falling edge of the clock signal, in a first transfer mode,

wherein the controller is configured to output data through at least one of the data terminals to the outside of the storage device, in accordance with both the rising edge and the falling edge of the clock signal, in a second transfer mode, and

wherein the controller is configured to receive and respond to commands via the command terminal in accordance with only one of a rising edge and a falling edge of the clock signal while outputting data through at least one of the data terminals to the outside of the storage device in accordance with both the rising edge and the falling edge of the clock signal, in the second transfer mode.

2. The storage device according to claim 1 ,

wherein the controller is configured to read data from the nonvolatile memory and output the read data through at least one of the data terminals.

3. The storage device according to claim 1 ,

wherein the nonvolatile memory is a semiconductor memory.

4. The storage device according to claim 3 ,

wherein the semiconductor memory is a NAND type flash memory.

5. The storage device according to claim 1 ,

wherein the controller is configured to output a second status data that includes information indicating that the storage device is set into the second transfer mode, through one of the data terminals to the outside of the storage device, in response to a second command.

6. The storage device according to claim 1 ,

wherein the data output in the first transfer mode is the first status data which includes data fields of a plurality of function groups, and

wherein the second transfer mode is assigned to one of the function groups.

7. The storage device according to claim 6 ,

wherein the number of the function groups is six.

8. The storage device according to claim 1 ,

wherein the first status data further includes information on a maximum consumption current required for the second transfer mode.

9. The storage device according to claim 1 ,

wherein the controller is configured to output data through at least one of the data terminals to the outside of the storage device, in accordance with the clock signal having a first frequency, in a normal bus mode,

wherein the controller is configured to output data through at least one of the data terminals to the outside of the storage device, in accordance with the clock signal having a second frequency, in a high-speed bus mode,

wherein the second frequency is higher than the first frequency, and

wherein the first status data further includes information indicating that the storage device supports the high-speed bus mode.

10. The storage device according to claim 1 ,

wherein the first status data further includes information indicating that the storage device supports an IC card function, and

wherein the controller is configured to validate the IC card function of the storage device in response to the second command.

11. The storage device according to claim 1 ,

wherein the first status data further includes information on a command status.

12. The storage device according to claim 1 ,

wherein the controller is configured to output a response to the first command through the command terminal to the outside of the storage device.

13. The storage device according to claim 1 ,

wherein the controller is configured to receive a second command through the command terminal from the outside of the storage device, and

wherein the controller is configured to stop outputting data through at least one of the data terminals to the outside of the storage device, in response to the second command.

14. The storage device according to claim 1 ,

wherein the controller is configured to output data in a plurality of data blocks, through at least one of the data terminals to the outside of the storage device, and

wherein a CRC code is added to each of the data blocks.

15. The storage device according to claim 1 ,

wherein the controller is configured to output data through all data terminals to the outside of the storage device, in a first bit mode, and

wherein the controller is configured to output data through only one of the data terminals to the outside of the storage device, in a second bit mode.

16. A memory card comprising:

a command terminal;

a plurality of data terminals;

a clock terminal;

a power terminal for a power supply voltage;

a ground terminal for a ground voltage;

a nonvolatile memory; and

a controller coupled to the command terminal, the data terminals, the clock terminal, the power terminal, and the ground terminal,

wherein the controller receives the clock signal through the clock terminal from the outside of the memory card,

wherein the controller outputs data through at least one of the data terminals to the outside of the memory card, in accordance with only one of a rising edge and a falling edge of the clock signal, in a first transfer mode,

wherein the controller outputs data through at least one of the data terminals to the outside of the memory card, in accordance with both the rising edge and the falling edge of the clock signal, in a second transfer mode,

wherein the controller receives a command and responds to the command via the command terminal in accordance with only one of a rising edge and a falling edge of the clock signal, and

wherein, only if the card supports a double-edge mode, the controller outputs data through at least one of the data terminals to the outside of the memory card in accordance with both the rising edge and the falling edge of the clock signal, in the second transfer mode.

17. The memory card according to claim 16 ,

wherein the controller reads data from the nonvolatile memory and outputs the read data through at least one of the data terminals.

18. The memory card according to claim 16 ,

wherein the nonvolatile memory is a semiconductor memory.

19. The memory card according to claim 18 ,

wherein the semiconductor memory is a NAND type flash memory.

20. The memory card according to claim 16 ,

wherein the controller outputs a second status data that includes information indicating that the memory card is set into the second transfer mode, through one of the data terminals to the outside of the memory card, in response to the second command.

21. The memory card according to claim 16 ,

wherein the first status data includes data fields of a plurality of function groups, and

wherein the second transfer mode is assigned to one of the function groups.

22. The memory card according to claim 21 ,

wherein the number of the function groups is six.

23. The memory card according to claim 16 ,

wherein the first status data further includes information on a maximum consumption current required for the second transfer mode.

24. The memory card according to claim 16 ,

wherein the controller outputs data through at least one of the data terminals to the outside of the memory card, in accordance with the clock signal having a first frequency, in a normal bus mode,

wherein the controller outputs data through at least one of the data terminals to the outside of the memory card, in accordance with the clock signal having a second frequency, in a high-speed bus mode,

wherein the second frequency is higher than the first frequency, and

wherein the first status data further includes information indicating that the memory card supports the high-speed bus mode.

25. The memory card according to claim 16 ,

wherein the first status data further includes information indicating that the memory card supports an IC card function, and

wherein the controller validates the IC card function of the memory card in response to the second command.

26. The memory card according to claim 16 ,

wherein the first status data further includes information on a command system.

27. The memory card according to claim 16 ,

wherein the controller outputs a response to the first command through the command terminal to the outside of the memory card.

28. The memory card according to claim 16 ,

wherein the controller receives a second command through the command terminal from the outside of the memory card, and

wherein the controller stops outputting data through at least one of the data terminals to the outside of the memory card, in response to the second command.

29. The memory card according to claim 16 ,

wherein the controller outputs data in a plurality of data blocks, through at least one of the data terminals to the outside of the memory card, and

wherein a CRC code is added to each of the data blocks.

30. The memory card according to claim 16 ,

wherein the controller outputs data through all data terminals to the outside of the memory card, in a first bit mode, and

wherein the controller outputs data through only one of the data terminals to the outside of the memory card, in a second bit mode.

Assignments (3)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
Priority Claims (1)
JP 2005-193002 · Jun 30, 2005 · national
Continuity (6)
Continuation 15263950 · Sep 13, 2016
Continuation 14508380 · Oct 7, 2014
Continuation 13005910 · Jan 13, 2011
Continuation 12351889 · Jan 12, 2009
Continuation 11476853 · Jun 29, 2006
Related Publication 20180074726A1 · Mar 15, 2018