Semiconductor device and manufacturing method thereof
In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, first recesses are formed in the first dielectric layer. Metal wirings extending is a first direction are formed in the first recesses. A mask layer is formed over the metal wirings and the first dielectric layer, which includes a first opening extending in the first direction and is located above a space between adjacent two metal wirings. A first groove corresponding to the first opening is formed between the adjacent two metal wirings by etching the first dielectric layer using the mask layer as an etching mask. A second dielectric layer is formed so that a first air gap is formed in the first groove. A width of the first opening in a perpendicular direction to the first direction is smaller than a space between the adjacent two metal wirings.
1. A semiconductor device, comprising:
a first dielectric layer disposed over a substrate;
metal wirings embedded in the first dielectric layer, the metal wirings extending in a first direction;
a second dielectric layer disposed over the first dielectric layer and the metal wirings;
an insulating layer disposed between the first dielectric layer and the second dielectric layer; and
an air gap formed between adjacent two metal wirings, wherein:
in a plan view, the insulating layer includes a slit under which the air gap is disposed, the slit has a width smaller than a space between the adjacent two metal wirings in a second direction crossing the first direction, and
upper surfaces of the adjacent two metal wirings are fully covered by the insulating layer.
2. The semiconductor device of claim 1 , wherein the upper surfaces of the adjacent two metal wirings are not in contact with the second dielectric layer.
3. The semiconductor device of claim 2 , wherein the first insulating layer overhangs a space between the adjacent two metal wirings in a cross sectional view.
4. The semiconductor device of claim 3 , wherein an amount of overhang is in a range from 0.5 nm to 2 nm.
5. The semiconductor device of claim 3 , wherein:
a groove is formed in the space between the adjacent two metal wirings,
the second dielectric layer includes a first etch-stop layer, a cap layer and an interlayer dielectric layer,
the first etch-stop layer is conformally formed in the groove, and
the cap layer is conformally formed on the first etch-stop layer, thereby defining at least a side and a bottom of the air gap.
6. The semiconductor device of claim 5 , wherein a part of the cap layer in the groove is not covered by the interlayer dielectric layer.
7. The semiconductor device of claim 1 , wherein the insulating layer is made of at least one selected from the group consisting of SiN, SiCO, SiCN and SiCON.
8. The semiconductor device of claim 6 , wherein a thickness of the insulating layer in a range of 1 nm to 30 nm.
9. A semiconductor device, comprising:
a first dielectric layer disposed over a substrate;
metal wirings embedded in the first dielectric layer, the metal wirings including a first metal wiring, a second metal wiring and a third metal wiring, all extending in a first direction and arranged in a second direction perpendicular to the first direction;
a second dielectric layer disposed over the first dielectric layer and the metal wirings;
an insulating layer disposed between the first dielectric layer and the second dielectric layer; and
a first air gap formed between the first metal wiring and the second metal wiring and a second air gap formed between the second metal wiring and the third metal wiring, wherein:
in a plan view, the insulating layer includes a first slit under which the first air gap is disposed and a second slit under which the second sir gap is disposed,
the first and second slits have a width smaller than a space between adjacent two metal wirings in a second direction crossing the first direction, and
upper surfaces of the first to third metal wirings are fully covered by the first insulating layer.
10. The semiconductor device of claim 9 , wherein the upper surfaces of the first to third metal wirings are not in contact with the second dielectric layer.
11. The semiconductor device of claim 9 , wherein:
a first groove is formed in the space between the first and second metal wirings, and a second groove is formed in the space between the second and third metal wirings,
the second dielectric layer includes a first etch-stop layer, a cap layer and an interlayer dielectric layer,
the first etch-stop layer is conformally formed in the first and second grooves,
the cap layer is conformally formed on the first etch-stop layer, and
a part of the cap layer in the first groove is not covered by the interlayer dielectric layer.
12. The semiconductor device of claim 11 , wherein the first insulating layer overhangs a space between adjacent two metal wirings in a cross sectional view.
13. The semiconductor device of claim 12 , wherein an amount of overhang is in a range from 0.5 nm to 2 nm.
14. The semiconductor device of claim 9 , wherein the insulating layer is made of at least one selected from the group consisting of SiN, SiCO, SiCN and SiCON.
15. The semiconductor device of claim 14 , wherein a thickness of the insulating layer in a range of 1 nm to 30 nm.
16. The semiconductor device of claim 9 , wherein a location of the first slit in the first direction is different from a location of the second slit in plan view.
17. A semiconductor device, comprising:
a first dielectric layer disposed over a substrate;
metal wirings embedded in the first dielectric layer, the metal wirings including a first metal wiring, a second metal wiring and a third metal wiring, all extending in a first direction and arranged in a second direction perpendicular to the first direction;
a second dielectric layer disposed over the first dielectric layer and the metal wirings;
an insulating layer disposed between the first dielectric layer and the second dielectric layer; and
a first air gap formed between the first metal wiring and the second metal wiring and a second air gap formed between the second metal wiring and the third metal wiring, wherein:
parts of upper surface of the first and second metal wirings are covered by the insulating layer, and
an upper surface of the second metal wiring has a region not covered by the insulating layer.
18. The semiconductor device of claim 17 , wherein:
a first groove is formed in the space between the first and second metal wirings, a second groove is formed in the space between the second and third metal wirings,
the second dielectric layer includes a first etch-stop layer, a cap layer and an interlayer dielectric layer,
the first etch-stop layer is conformally formed in the first and second grooves,
the cap layer is conformally formed on the first etch-stop layer, and
the cap layer in the first groove is covered by the interlayer dielectric layer.
19. The semiconductor device of claim 18 , wherein the first etch-stop layer is in contact with the upper surface of the second metal wiring.
20. The semiconductor device of claim 18 , wherein the upper surfaces of the first and third metal wirings has a step.