IP Library › Granted Patent US 10,541,191
Granted Patent B2
US 10,541,191 · App. 15/816,913 · Granted Jan 21, 2020

Elbow contact for field-effect transistor and manufacture thereof

Inventors: Guy Cohen (Yorktown Heights, NY); Christian Lavoie (Yorktown Heights, NY); Ahmet Serkan Ozcan (San Jose, CA); Paul Solomon (Yorktown Heights, NY)
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
H01L23/48H01L21/02008H01L21/4885H01L21/7688
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Quick Facts
Patent No.
US 10,541,191
App. No.
15/816,913
Granted
Jan 21, 2020
Kind
B2
Abstract

A field-effect transistor (FET) and method of manufacture thereof include a gate, a doped semiconductor structure formed on top of the planar source and drain regions, and a sheath of conducting materials flanking the formed doped semiconductor structure, where the sheath is perpendicular to a surface of the planar source and drain regions.

Claims (20)

1. A field-effect transistor (FET) including planar source and drain regions, the FET comprising:

a gate;

a doped semiconductor structure formed on top of the planar source and drain regions; and

a sheath of conducting materials flanking the doped semiconductor structure,

wherein the sheath is perpendicular to a surface of the planar source and drain regions,

wherein the sheath is bent up, out of plane alongside the gate, to thereby increase a contact area,

wherein more than one sheath are present per contact of the doped semiconductor structure,

wherein the planar source and drain regions include a trench,

wherein the trench includes an elongated pillar extending in a direction of growth through the trench,

wherein a core of the trench is removed and replaced with a metal, and

wherein an outside of the elongated pillar includes a metal coating.

2. The FET of claim 1 , wherein the sheath is alongside the gate, and

wherein the sheath is vertical.

3. The FET of claim 1 , wherein the doped semiconductor structure is formed by one of:

epitaxial growth;

etching a highly doped Si region; and

recrystallizing a highly doped amorphous semiconductor region.

4. The FET of claim 1 , wherein the sheath increases the contact area between the doped semiconductor structure and an upper metallization thereby lowering a contact resistance.

5. The FET of claim 1 , wherein the sheath has a non-uniform thickness.

6. The FET of claim 1 , wherein the sheath flanks both sides of the doped semiconductor structure.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 20, 2017
From: COHEN, GUY; LAVOIE, CHRISTIAN; OZCAN, AHMET SERKAN; SOLOMON, PAUL
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 044488/0190 →
Continuity (1)
Related Publication 20190157187A1 · May 23, 2019