Semiconductor arrangement with capacitor and method of fabricating the same
A semiconductor arrangement includes an active region including a semiconductor device. The semiconductor arrangement includes a capacitor. The capacitor includes a first electrode over at least one dielectric layer over the active region. The first electrode surrounds an open space within the capacitor. The first electrode has a non-linear first electrode sidewall.
1. A method of forming a semiconductor arrangement comprising:
forming a bit line in a first, single, dielectric layer over an active region of the semiconductor arrangement and a first metal structure in the first, single, dielectric layer;
forming a second dielectric layer over the first, single, dielectric layer, wherein a second metal structure is embedded in the second dielectric layer;
forming a first opening by removing the second metal structure, wherein the first metal structure is exposed through the first opening;
forming a first electrode, of a capacitor, in the first opening to overlie the first metal structure;
forming an insulating layer, of the capacitor, in the first opening over the first electrode; and
forming a second electrode, of the capacitor, in the first opening over the insulating layer.
2. The method of claim 1 , comprising:
forming an etch stop layer over the first, single, dielectric layer before forming the second dielectric layer, wherein the forming a first opening comprises:
removing a portion of the etch stop layer overlying the first metal structure to expose the first metal structure.
3. The method of claim 1 , comprising:
forming a third dielectric layer over the second dielectric layer, wherein a third metal structure is embedded in the third dielectric layer and overlies the second metal structure.
4. The method of claim 3 , wherein the forming a first opening comprises:
removing the third metal structure such that the first opening is defined by a sidewall of the second dielectric layer and a sidewall of the third dielectric layer.
5. The method of claim 4 , wherein the forming a first electrode comprises:
forming the first electrode to contact the sidewall of the second dielectric layer and the sidewall of the third dielectric layer.
6. The method of claim 1 , comprising:
forming an etch stop layer over the second electrode, wherein an empty space is defined between the etch stop layer and the second electrode.
7. The method of claim 1 , comprising:
etching the second electrode and the insulating layer to expose a sidewall of the insulating layer.
8. The method of claim 7 , comprising:
forming an etch stop layer over the second electrode, wherein the etch stop layer directly contacts the sidewall of the insulating layer.
9. The method of claim 8 , comprising:
forming a pickup contact, wherein the pickup contact extends through the etch stop layer and contacts the second electrode.
10. The method of claim 1 , comprising:
performing a dual damascene process on the second dielectric layer to define a second opening, and
filling the second opening with metal to form the second metal structure.
11. The method of claim 1 , wherein a portion of the first opening remains after the forming a second electrode in the first opening.
12. A method of forming a semiconductor arrangement comprising:
forming a first dielectric layer, wherein a first metal structure is embedded in the first dielectric layer;
forming a first opening by removing the first metal structure;
forming a first electrode, of a capacitor, in the first opening;
forming an insulating layer, of the capacitor, in the first opening over the first electrode;
forming a second electrode, of the capacitor, in the first opening over the insulating layer;
etching the second electrode and the insulating layer to expose a sidewall of the insulating layer; and
forming an etch stop layer over the second electrode, wherein the etch stop layer directly contacts the sidewall of the insulating layer.
13. The method of claim 12 , wherein the etch stop layer caps the first opening.
14. The method of claim 12 , wherein a void is defined between the etch stop layer and the second electrode.
15. The method of claim 12 , wherein the forming a first opening comprises:
exposing a second metal structure embedded in a second dielectric layer underlying the first dielectric layer.
16. The method of claim 15 , wherein the forming a first electrode comprises forming the first electrode to contact the second metal structure.
17. The method of claim 12 , comprising:
performing a dual damascene process on the first dielectric layer to define a second opening, and
filling the second opening with metal to form the first metal structure.
18. The method of claim 12 , wherein the forming an etch stop layer comprises:
forming the etch stop layer to contact a top surface and a sidewall of the second electrode.
19. The method of claim 12 , comprising:
forming a second dielectric layer over the first dielectric layer, wherein:
a second metal structure is embedded in the second dielectric layer, and
the forming a first opening comprises:
forming the first opening by removing the second metal structure.
20. A method of forming a semiconductor arrangement comprising:
forming a stacked arrangement of metal structures in a set of dielectric layers;
removing the metal structures to define an opening extending through the set of dielectric layers;
forming a first electrode, of a capacitor, in the opening;
forming an insulating layer, of the capacitor, in the opening over the first electrode;
forming a second electrode, of the capacitor, in opening over the insulating layer; and
forming a layer over the opening to cap the opening, wherein an empty space is defined between the layer and the second electrode.