Gate-all-around fin device
A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.
1. A method comprising:
forming a central well of a first conductivity type located in a substrate of the first conductivity type;
forming a doped well ring of a second conductivity type in the substrate and enclosing the central well of the first conductivity type;
forming a doped well region in the substrate adjacent the doped well ring, wherein the doped well ring is interposed between the doped well region and the central well;
forming a first doped fin contact region of the first conductivity type to form a source contact for a first fin to form a source located over the central well of the first conductivity type; and
forming a second doped fin contact region of the second conductivity type to form drain contact regions for a second fin to form a drain located over the doped well ring, wherein the drain contact regions include alternating p regions and n regions formed directly on the second fin.
2. The method of claim 1 , further comprising forming a gate structure over the central well and around the first fin, wherein the gate structure is in a dielectric fill material.
3. The method of claim 2 , wherein the doped well is of the first conductivity type.
4. The method of claim 3 , wherein:
the first conductivity type is formed as a deep N-well and the second conductivity type as a P-well; and
the gate structure is formed partially over the deep N-well and the P-well.
5. The method of claim 4 , wherein the deep N-well is formed as a ring surrounding the P-well.
6. The method of claim 3 , wherein:
the first conductivity type is formed as a continuous deep N-well and the second conductivity type as a P-well; and
the gate structure is formed completely over the deep N-well.
7. The method of claim 3 , wherein:
the first conductivity type is formed as a shallow N-well and the second conductivity type is a P-well;
the gate structure is formed partially over the shallow N-well and the P-well; and
the shallow N-well is formed as a ring structure.
8. The method of claim 3 , wherein:
the first conductivity type is formed as a continuous shallow N-well and the second conductivity type as a P-well;
the gate structure is formed entirely over the shallow N-well; and
the first fin structure comprising the source contact is formed completely over the shallow N-well.
9. The method of claim 2 , wherein the gate structure is formed over an insulating layer above the central well and is formed vertically around the first fin.
10. The method of claim 2 , wherein the first doped fin contact region is formed to extend over both an upper surface of the gate structure and an upper surface of the first fin.
11. The method of claim 1 , further comprising forming a shallow trench isolation (STI) structure in the doped well ring.
12. The method of claim 11 , wherein a first portion of the STI structure is formed between the first fin and the second fin.
13. The method of claim 12 , wherein a second portion of the STI structure is in contact with a portion of the second fin and extends over the doped well region.
14. The method of claim 13 , wherein the first portion of the STI structure is formed to extend into the doped well ring and under a lower portion of the gate structure.
15. The method of claim 1 , further comprising forming the first fin and the second fin using sidewall image transfer (SIT) techniques.
16. The method of claim 15 , further comprising using an implantation process to form the source and the drain.