Hardware description language specification translator

1. A method, comprising:

inputting a hardware description language (HDL) specification of a circuit design to a programmed processor;

generating by the programmed processor a design graph of the circuit design from the HDL specification;

determining matches between interfaces and modules of the HDL specification and interfaces and blocks in a library of graphical design objects by the programmed processor; and

translating by the programmed processor, the design graph into a data model that describes matching blocks, interfaces from the library, and connections between the blocks based on the matches determined between modules of the HDL specification and blocks of the library, wherein the data model is compatible with a graphical design environment and has data that specify graphical blocks that correspond to the modules of the HDL specification and data that specify graphical lines that correspond to signal communications between the modules, and the graphical blocks and graphical lines are user configurable.

2. The method of claim 1 , wherein the determining matches includes determining matches between meta-data associated with the modules in the design graph and metadata associated with blocks in the library.

3. The method of claim 2 , wherein the determining includes determining matches between metadata associated with pins of the design graph and metadata associated with interfaces in the library.

4. The method of claim 3 , wherein the determining includes determining matches between a first prefix of names of pins of the design graph and a second prefix of names of interfaces in the library.

5. The method of claim 1 , wherein the determining includes:

identifying an interface type in the library for each module of the design graph;

substituting the identified interface type in a boundary of each module;

determining a match between a tag associated with each module to a unique identifier of a block type in the library;

in response to determining a match between the tag and the unique identifier, performing a design rule check; and

in response to determining absence of a match between the tag and the unique identifier, performing a module-inference.

6. The method of claim 5 , wherein performing the module-inference includes adding a block to the library having a definition of the module.

7. The method of claim 1 , further comprising performing a syntax and semantics check on the design graph prior to the determining.

8. The method of claim 1 , further comprising generating an intermediate design graph of the circuit design based on connections specified in the design graph and blocks of the library determined to match the modules of the HDL specification.

9. The method of claim 1 , wherein the translating includes:

traversing and querying properties of blocks of the design graph; and

constructing, querying, and setting objects in the data model.

10. The method of claim 1 , further comprising:

generating from the data model, configuration data for implementing the circuit design; and

configuring a programmable IC with the configuration data to implement the circuit design on the programmable IC.

11. A system, comprising:

a processor; and

a memory and storage arrangement coupled to the processor, wherein the memory and storage arrangement is configured with instructions that when executed by the processor cause the processor to perform operations including:

inputting an hardware description language (HDL) specification of a circuit design;

generating a design graph of the circuit design from the HDL specification;

determining matches between interfaces and modules of the HDL specification and interfaces and blocks in a library; and

translating the design graph into a data model that describes matching blocks, interfaces from the library, and connections between the blocks based on the matches determined between modules of the HDL specification and blocks of the library, wherein the data model is compatible with a graphical design environment and has data that specify graphical blocks that correspond to the modules of the circuit design and lines that correspond to signal communications between the modules, and the graphical blocks and graphical lines are user configurable.

12. The system of claim 11 , wherein the memory and storage arrangement is further configured with instructions that when executed by the processor cause the processor to determine the matches by:

determining matches between metadata associated with the modules in the design graph and metadata associated with blocks in the library.

13. The system of claim 12 , wherein the memory and storage arrangement is further configured with instructions that when executed by the processor cause the processor to determine the matches by:

determining matches between metadata associated with pins of the design graph and metadata associated with interfaces in the library.

14. The system of claim 13 , wherein the memory and storage arrangement is further configured with instructions that when executed by the processor cause the processor to determine the matches by:

determining matches between a first prefix of names of pins of the design graph and a second prefix of names of interfaces in the library.

15. The system of claim 11 , wherein the memory and storage arrangement is further configured with instructions that when executed by the processor cause the processor to determine the matches by:

identifying an interface type in the library for each module of the design graph;

substituting the identified interface type in a boundary of each module;

determining a match between a tag associated with each module to a unique identifier of a block type in the library;

in response to determining a match between the tag and the unique identifier, performing a design rule check; and

in response to determining absence of a match between the tag and the unique identifier, performing a module-inference.

16. The system of claim 15 , wherein the memory and storage arrangement is further configured with instructions that when executed by the processor cause the processor to perform the module-inference by:

adding a block to the library having a definition of the module.

17. The system of claim 11 , wherein the memory and storage arrangement is further configured with instructions that when executed by the processor cause the processor to:

perform a syntax and semantics check on the design graph prior to the determining.

18. The system of claim 11 , wherein the memory and storage arrangement is further configured with instructions that when executed by the processor cause the processor to:

generate an intermediate design graph of the circuit design based on connections specified in the design graph and blocks of the library determined to match the modules of the HDL specification.

19. The system of claim 11 , wherein the memory and storage arrangement is further configured with instructions that when executed by the processor cause the processor to translate the design graph by:

traversing and querying properties of blocks of the design graph; and

constructing, querying, and setting objects in the data model.

20. The system of claim 11 , wherein the memory and storage arrangement is further configured with instructions that when executed by the processor cause the processor to:

generate from the data model, configuration data for implementing the circuit design; and

configure a programmable IC with the configuration data to implement the circuit design on the programmable IC.