IP Library Granted Patent US 10,290,556
Granted Patent B2
US 10,290,556 · App. 15/823,744 · Granted May 14, 2019

High reliability wafer level semiconductor packaging

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Quick Facts
Patent No.
US 10,290,556
App. No.
15/823,744
Granted
May 14, 2019
Kind
B2
Abstract

Implementations of semiconductor packages may include: a semiconductor wafer, a glass lid fixedly coupled to a first side of the semiconductor die by an adhesive, a redistribution layer coupled to a second side of the semiconductor die, and a plurality of ball mounts coupled to the redistribution layer on a side of the redistribution layer coupled to the semiconductor die. The adhesive may be located in a trench around a perimeter of the semiconductor die and located in a corresponding trench around a perimeter of the glass lid.

Claims (25)

1. A semiconductor package comprising:

a semiconductor die comprising a first side and a second side;

a first trench comprised in the first side of the semiconductor die, the trench positioned outside an active area of the die;

a glass lid comprising a second trench, the glass lid fixedly coupled to a first side of the semiconductor die by an adhesive;

wherein the adhesive is comprised in the first trench in the first side of the semiconductor die and simultaneously comprised in the second trench positioned around a perimeter of the glass lid;

wherein the adhesive does not cover any edge of the semiconductor die.

2. The semiconductor package of claim 1 , wherein the adhesive is selected from the group consisting of thermal curable resin, epoxy, ultraviolet light curable resin and any combination thereof.

3. The semiconductor package of claim 2 , wherein the adhesive is cured.

4. The semiconductor package of claim 1 , wherein the adhesive is evenly distributed within the first trench and the second trench.

5. The semiconductor package of claim 1 , wherein the adhesive extends out from the first trench and the second trench to further bond the glass lid and the semiconductor die.

6. The semiconductor package of claim 1 , further comprising a redistribution layer coupled to the second side of the semiconductor die.

7. The semiconductor package of claim 6 , further comprising a plurality of ball mounts coupled to the redistribution layer on a side of the redistribution layer opposing the side of the redistribution layer coupled to the semiconductor die.

8. A semiconductor package comprising:

a semiconductor die comprising a first side and a second side;

a first trench comprised around the perimeter of the first side of the semiconductor die; and

a glass lid fixedly coupled to a first side of the semiconductor die by an adhesive, the adhesive comprised in a second trench around a perimeter of the glass lid;

wherein the adhesive is simultaneously comprised in the first trench and the second trench, the trenches comprising corresponding locations in the semiconductor die and the glass lid;

wherein the adhesive does not cover any edge of the semiconductor die.

9. The semiconductor package of claim 8 , wherein the adhesive is selected from the group consisting of thermal curable resin, epoxy, ultraviolet light curable resin and any combination thereof.

10. The semiconductor package of claim 9 , wherein the adhesive is cured.

11. The semiconductor package of claim 8 , wherein the adhesive is evenly distributed within the first trench and the second trench.

12. The semiconductor package of claim 8 , wherein the adhesive extends out from the first trench and the second trench to further bond the glass lid and the semiconductor die.

13. The semiconductor package of claim 8 , further comprising:

a redistribution layer coupled to a second side of the semiconductor die; and

a plurality of ball mounts coupled to the redistribution layer on a side of the redistribution layer opposing the side of the redistribution layer coupled to the semiconductor die.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 046530, FRAME 0494 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064159/0524 →
PATENT SECURITY AGREEMENT Recorded Jul 11, 2018
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 046530/0494 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 28, 2017
From: HSIEH, YU-TE
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 044232/0284 →