Semiconductor structure, static random access memory, and fabrication method thereof

1. A method for fabricating a semiconductor structure, comprising:

providing a base substrate, including a substrate and a plurality of discrete fins on the substrate, wherein the substrate includes a pull-up transistor region and a pull-down transistor region adjacent to the pull-up transistor region;

forming a gate structure, across a length portion of each fin, covering top and sidewall surfaces of each fin, and on each fin;

forming pull-up doped epitaxial layers, in the fin on both sides of the gate structure in the pull-up transistor region;

forming a first pull-down doped region and a second pull-down doped region, in the fin on two sides of the gate structure in the pull-down transistor region, respectively, wherein:

the first pull-down doped region is an epitaxial region connected to the pull-up doped epitaxial layer; and

the second pull-down doped region is a non-epitaxial region formed by performing an ion-doped non-epitaxial layer process on the fin.

2. The method according to claim 1 , wherein:

the pull-up transistor region includes a PMOS region;

the pull-down transistor region includes an NMOS region;

doped ions in the pull-up doped epitaxial layers include P-type ions; and

doped ions in the first pull-down doped region and the second pull-down doped region include N-type ions.

3. The method according to claim 1 , wherein a process for forming the pull-up doped epitaxial layers includes:

an in-situ doped selective epitaxial process, including:

forming pull-up epitaxial layers in the fin on both sides of the gate structure in the pull-up transistor region, and

in-situ self-doping P-type ions during the process for forming the pull-up epitaxial layers.

4. The method according to claim 3 , wherein:

the pull-up doped epitaxial layers are made of silicon doped with Ge ions; and

a concentration of the Ge ions in the pull-up doped epitaxial layers is in a range of approximately 5.02×10 21 atoms/cm 3 -2.5×10 22 atoms/cm 3 .

5. The method according to claim 1 , wherein forming the second pull-down doped region includes:

performing an N-type ion implantation process on the fin on another side of the gate structure in the pull-down transistor region.

6. The method according to claim 5 , wherein parameters of the N-type ion implantation process include:

implanted ions of P ions, having implantation ion energy in a range of approximately 1KeV -4 KeV, and an implantation ion dose in a range of approximately 1×10 15 atoms/cm 3 -2 ×10 15 atoms/cm 3 ; or

implanted ions of As ions, having implantation ion energy in a range of approximately 1 KeV -4 KeV, and an implantation ion dose in a range of approximately 1×10 15 atoms/cm 3 -4×10 15 atoms/cm 3 .

7. The method according to claim 1 , wherein a process for forming the first pull-down doped region includes:

an in-situ doped selective epitaxial process, including:

forming a pull-down epitaxial layer in the fin on one side of the gate structure in the pull-down transistor region, and

in-situ self-doping N-type ions when forming the pull-down epitaxial layer.

8. The method according to claim 7 , wherein:

the first pull-down doped region is made of silicon doped with P ions; and

a concentration of the P ions in the first pull-down doped region is in a range of approximately 1×10 20 atoms/cm 3 -2×10 21 atoms/cm 3 .

9. The method according to claim 1 , wherein forming the pull-up doped epitaxial layers, the first pull-down doped region and the second pull-down doped region includes:

forming a P-region mask layer, on top and sidewalls of the fin in the pull-up transistor region, wherein the P-region mask layer is formed on top and sidewalls of the fin in the pull-down transistor region;

forming a P-region trench, in the fin on both sides of the gate structure in the pull-up transistor region, by etching the P-region mask layer on the top of the fin in the pull-up transistor region and etching portions of a thickness of the fin in the pull-up transistor region, wherein the etched fin in the pull-up transistor region is coplanar with a top of the P-region mask layer;

forming the pull-up doped epitaxial layers in the P-region trench;

forming an N-region mask sidewall spacer, on the P-region mask layer in the pull-down transistor region after forming the pull-up doped epitaxial layers, wherein the N-region mask sidewall spacer and the P-region mask layer in the pull-down transistor region serve as an N-region mask layer;

forming an N-region trench, in the fin on one side of the gate structure in the pull-down transistor region, by etching the N-region mask layer on top of the fin on one side of the gate structure in the pull-down transistor region and etching portions of a thickness of the fin on one side of the gate structure in the pull-down transistor region, wherein the etched fin in the pull-down transistor region is coplanar with a top of the N-region mask layer;

forming the first pull-down doped region, by forming a pull-down epitaxial layer in the N-region trench, and in-situ self-doping N-type ions during the process for forming the pull-down epitaxial layer;

forming a patterned layer, covering the pull-up transistor region and the first pull-down doped region, and exposing the N-region mask layer on the top of the fin on the other side of the gate structure in the pull-down transistor region; and

forming the second pull-down doped region, in the fin on the other side of the gate structure in the pull-down transistor region by performing an ion doping process on the N-region mask layer with the patterned layer as a mask.

10. The method according to claim 1 , wherein:

the pull-down transistor region includes a first pull-down transistor region and a second pull-down transistor region adjacent to the first pull-down transistor region, and the first pull-down transistor region is adjacent to the pull-up transistor region;

the gate structure in the first pull-down transistor region is across a length portion of the fin in the first pull-down transistor region, and the gate structure in the second pull-down transistor region is across a length portion of the fin in the second pull-down transistor region;

the first pull-down doped region in the fin on one side of the gate structure in the first pull-down transistor region is formed by performing an in-situ doped selective epitaxial process;

the second pull-down doped region in the fin on the other side of the gate structure in the first pull-down transistor region is formed by performing the ion-doped non-epitaxial layer process; and

third pull-down doped regions in the fin on both sides of the gate structure in the second pull-down transistor region are formed when performing the in-situ doped selective epitaxial process, wherein the third pull-down doped regions are made of the same material as the first pull-down doped region.

11. A method for fabricating a semiconductor structure, comprising: providing a base substrate, including a substrate and a plurality of discrete fins on the substrate, wherein the substrate includes a pull-up transistor region and a pull-down transistor region adjacent to the pull-up transistor region;

performing a pull-down threshold adjustment implantation treatment on the base substrate corresponding to the second pull-down doped region;

forming a gate structure, across a length portion of each fin, covering top and sidewall surfaces of each fin, and on each fin;

forming pull-up doped epitaxial layers, in the fin on both sides of the gate structure in the pull-up transistor region;

forming a first pull-down doped region, in the fin on one side of the gate structure in the pull-down transistor region, wherein the first pull-down doped region is connected to an adjacent pull-up doped epitaxial layer; and

forming a second pull-down doped region, in the fin on another side of the gate structure in the pull-down transistor region, wherein the second pull-down doped region is formed by performing an ion-doped non-epitaxial layer process on the fin.

12. The method according to claim 11 , wherein parameters of the pull-down threshold adjustment implantation treatment include:

doped ions including N-type ions;

implantation ion energy in a range of approximately 1 KeV -10 KeV; and

an implantation ion dose in a range of approximately 1×10 13 atoms/cm 3 -5×10 14 atoms/cm 3 .

13. The method according to claim 11 , wherein:

the pull-up transistor region includes a PMOS region;

the pull-down transistor region includes an NMOS region;

doped ions in the pull-up doped epitaxial layers include P-type ions; and

doped ions in the first pull-down doped region and the second pull-down doped region include N-type ions.

14. The method according to claim 11 , wherein a process for forming the pull-up doped epitaxial layers includes:

an in-situ doped selective epitaxial process, including:

forming pull-up epitaxial layers in the fin on both sides of the gate structure in the pull-up transistor region, and

in-situ self-doping P-type ions during the process for forming the pull-up epitaxial layers.

15. The method according to claim 14 , wherein:

the pull-up doped epitaxial layers are made of silicon doped with Ge ions; and

a concentration of the Ge ions in the pull-up doped epitaxial layers is in a range of approximately 5.02×10 21 atoms/cm 3 -2.5×10 22 atoms/cm 3 .

16. The method according to claim 11 , wherein forming the second pull-down doped region includes:

performing an N-type ion implantation process on the fin on another side of the gate structure in the pull-down transistor region.

17. The method according to claim 16 , wherein parameters of the N-type ion implantation process include:

implanted ions of P ions, having implantation ion energy in a range of approximately 1 KeV -4 KeV, and an implantation ion dose in a range of approximately 1×10 15 atoms/cm 3 -2×10 15 atoms/cm 3 ; or

implanted ions of As ions, having implantation ion energy in a range of approximately 1 KeV -4 KeV, and an implantation ion dose in a range of approximately 1×10 15 atoms/cm 3 -4×10 15 atoms/cm 3 .

18. The method according to claim 11 , wherein a process for forming the first pull-down doped region includes:

an in-situ doped selective epitaxial process, including:

forming a pull-down epitaxial layer in the fin on one side of the gate structure in the pull-down transistor region, and

in-situ self-doping N-type ions when forming the pull-down epitaxial layer.

19. The method according to claim 18 , wherein:

the first pull-down doped region is made of silicon doped with P ions; and

a concentration of the P ions in the first pull-down doped region is in a range of approximately 1×10 20 atoms/cm 3 -2×10 21 atoms/cm 3 .