Semiconductor structure including plurality of chips along with air gap and manufacturing method thereof
The present disclosure provides a semiconductor structure including a first chip having a first dielectric surface, a second chip having a second dielectric surface facing the first dielectric surface and maintaining a distance thereto, and an air gap between the second dielectric surface and the first dielectric surface. The first chip includes a plurality of first conductive lines in proximity to the first dielectric surface and parallel to each other, two adjacent first conductive lines each having a sidewall partially exposed from the first dielectric surface. The present disclosure further provides a method for manufacturing the semiconductor structure described herein.
1. A semiconductor structure, comprising:
a first chip having a first dielectric surface, the first chip comprising:
a plurality of first conductive lines in proximity to the first dielectric surface and parallel to each other, two adjacent first conductive lines of the plurality of first conductive lines, each having a sidewall partially exposed and protruding from the first dielectric surface;
a second chip having a second dielectric surface facing the first dielectric surface and maintaining a distance thereto; and
an air gap between the second dielectric surface and the first dielectric surface, wherein an entire top surface of the plurality of first conductive lines is exposed to the air gap, wherein the entire top surface of the plurality of first conductive lines is planar surface with each other.
2. The semiconductor structure of claim 1 , further comprising a first inner conductive line under the first dielectric surface.
3. The semiconductor structure of claim 2 , further comprising a second inner conductive line above the second dielectric surface.
4. The semiconductor structure of claim 3 , wherein the first inner conductive line and the second inner conductive line are electrically connected by a microbump.
5. The semiconductor structure of claim 4 , wherein a height of the microbump is from about 0.3 μm to about 5 μm.
6. The semiconductor structure of claim 1 , further comprising a protection layer laterally sealing the air gap.
7. The semiconductor structure of claim 6 , wherein the protection layer further covers the second chip.
8. The semiconductor structure of claim 1 , wherein a size of the second chip is smaller than a size of the first chip from a top view perspective.
9. The semiconductor structure of claim 1 , further comprising a second conductive line exposed from the second dielectric surface.
10. The semiconductor structure of claim 9 , wherein the second conductive line has a sidewall exposed from the second dielectric surface.
11. The semiconductor structure of claim 1 , further comprising a third conductive line in proximity to the first dielectric surface and having a surface exposed from the first dielectric surface, and a fourth conductive line in proximity to the second dielectric surface and having a surface exposed from the second dielectric surface, wherein the third conductive line and the fourth conductive line projectively correspond to each other.
12. The semiconductor structure of claim 11 , wherein the third conductive line comprises a sidewall exposed from the first dielectric surface.
13. The semiconductor structure of claim 1 , wherein the sidewall of the two adjacent first conductive lines exposed from the first dielectric surface is in contact with the air gap.
14. A semiconductor structure, comprising:
a first chip having a first dielectric surface, the first chip comprising:
a first conductive line in proximity to the first dielectric surface;
a second chip having a second dielectric surface facing the first dielectric surface and maintaining a distance thereto, the second chip comprising:
a second conductive line in proximity to the second dielectric surface; and
an air gap between the second dielectric surface and the first dielectric surface, the air gap having a width at least substantially equal to a width of the second chip,
wherein the first conductive line is protruding from the first dielectric surface thereby exposing a sidewall and an entire top surface of the first conductive line to the air gap, wherein the entire top surface of the first conductive line has a planar surface.
15. The semiconductor structure of claim 14 , further comprising a protection layer laterally sealing the air gap.
16. A semiconductor structure, comprising:
a first chip having a first dielectric surface, the first chip comprising:
a first inner conductive line under the first dielectric surface;
a second chip having a second dielectric surface facing the first dielectric surface and maintaining a distance thereto, the second chip comprising:
a second inner conductive line above the second dielectric surface;
a microbump having a height from about 0.3 μm to about 5 μm electrically connecting the first inner conductive line and the second inner conductive line;
an air gap between the second dielectric surface and the first dielectric surface;
a protection layer laterally sealing the air gap; and
a first conductive line protruding from the first dielectric surface, wherein an entire top surface of the first conductive line is exposed to the air gap, wherein the entire top surface of the first conductive line has a planar surface.
17. The semiconductor structure of claim 16 , further comprising:
a plurality of first conductive lines in proximity to the first dielectric surface and parallel to each other, two adjacent first conductive lines of the plurality of first conductive lines, each having a sidewall partially exposed from the first dielectric surface.
18. The semiconductor structure of claim 17 , further comprising a second conductive line exposed from the second dielectric surface.
19. The semiconductor structure of claim 16 , wherein the protection layer is composed of tetraethoxysilane (TEOS) or nitrides.