IP Library Granted Patent US 10,269,903
Granted Patent B2
US 10,269,903 · App. 15/826,576 · Granted Apr 23, 2019

Semiconductor structure having graded transition bodies

Inventor: Michael A. Briere (Scottsdale, AZ)
Assignee: Infineon Technologies Americas Corp.
H01L29/2003H01L21/0237H01L21/0251H01L21/0254H01L21/02381H01L21/02458H01L21/02488H01L21/02505H01L29/151H01L29/205H01L29/778H01L29/7786
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Quick Facts
Patent No.
US 10,269,903
App. No.
15/826,576
Granted
Apr 23, 2019
Kind
B2
Abstract

A semiconductor structure includes a substrate, a first graded transition body over the substrate, a second transition body and a III-Nitride semiconductor layer over the second transition body. The first graded transition body has a first lattice parameter at a first surface and a second lattice parameter at a second surface opposite the first surface. The second transition body has a smaller lattice parameter at a lower surface overlying the second surface of the first graded transition body and a larger lattice parameter at an upper surface of the second transition body. The second transition body includes at least two transition modules each having at least three interlayers. The first graded transition body and the second transition body reducing strain for the semiconductor structure.

Claims (43)

1. A semiconductor structure, comprising:

a substrate;

a first graded transition body over the substrate, the first graded transition body having a first lattice parameter at a first surface and a second lattice parameter at a second surface opposite the first surface;

a second transition body having a smaller lattice parameter at a lower surface overlying the second surface of the first graded transition body and a larger lattice parameter at an upper surface of the second transition body, the second transition body including at least two transition modules each having at least three interlayers; and

a III-Nitride semiconductor layer over the second transition body,

wherein the first graded transition body and the second transition body reduce strain for the semiconductor structure,

wherein the first graded transition body and the second transition body are each Nitride-based transition bodies.

2. The semiconductor structure of claim 1 , wherein the at least two transition modules are substantially the same.

3. The semiconductor structure of claim 1 , wherein the at least two transition modules have at least one of the at least three interlayers in common.

4. The semiconductor structure of claim 1 , wherein the at least two transition modules are different.

5. The semiconductor structure of claim 1 , wherein the substrate is a non-III-Nitride substrate.

6. The semiconductor structure of claim 1 , wherein the III-Nitride semiconductor layer comprises a fabricated device.

7. The semiconductor structure of claim 6 , wherein the fabricated device is a high electron mobility transistor (HEMT).

8. The semiconductor structure of claim 1 , wherein the substrate is a group IV substrate.

9. The semiconductor structure of claim 1 , wherein the substrate is a silicon substrate.

10. The semiconductor structure of claim 1 , further comprising a strain absorbing layer between the substrate and the first graded transition body.

11. The semiconductor structure of claim 10 , further comprising an intermediate layer comprising AlN formed between the strain absorbing layer and the first graded transition body.

12. The semiconductor structure of claim 1 , wherein the second transition body is formed directly on the second surface of the first graded transition body.

13. The semiconductor structure of claim 1 , wherein the at least three interlayers of the at least two transition modules of the second transition body each comprise Al x In y Ga (1-x-y) N.

14. The semiconductor structure of claim 1 , wherein the at least two transition modules of the second transition body have a different number of interlayers.

15. A semiconductor structure, comprising:

a substrate;

a first graded transition body over the substrate, the first graded transition body having a first lattice parameter at a first surface and a second lattice parameter at a second surface opposite the first surface;

a second transition body having a smaller lattice parameter at a lower surface overlying the second surface of the first graded transition body and a larger lattice parameter at an upper surface of the second transition body, the second transition body including at least two transition modules each having at least three interlayers; and

a III-Nitride semiconductor layer over the second transition body,

wherein the first graded transition body and the second transition body reduce strain for the semiconductor structure,

wherein the first graded transition body is a III-Nitride graded transition body comprising two or more interlayers.

16. A semiconductor structure, comprising:

a substrate;

a first graded transition body over the substrate, the first graded transition body having a first lattice parameter at a first surface and a second lattice parameter at a second surface opposite the first surface;

a second transition body having a smaller lattice parameter at a lower surface overlying the second surface of the first graded transition body and a larger lattice parameter at an upper surface of the second transition body, the second transition body including at least two transition modules each having at least three interlayers; and

a III-Nitride semiconductor layer over the second transition body,

wherein the first graded transition body and the second transition body reduce strain for the semiconductor structure,

wherein the first graded transition body is formed of a single layer of AlGaN.

17. A semiconductor structure, comprising:

a substrate;

a first graded transition body over the substrate, the first graded transition body having a first lattice parameter at a first surface and a second lattice parameter at a second surface opposite the first surface;

a second transition body having a smaller lattice parameter at a lower surface overlying the second surface of the first graded transition body and a larger lattice parameter at an upper surface of the second transition body, the second transition body including at least two transition modules each having at least three interlayers; and

a III-Nitride semiconductor layer over the second transition body,

wherein the first graded transition body and the second transition body reduce strain for the semiconductor structure,

wherein the first graded transition body comprises a first interlayer and a second interlayer formed on the first interlayer,

wherein the first interlayer of the first graded transition body has a smaller lattice parameter than the second interlayer of the first graded transition body,

wherein the first interlayer of the first graded transition body has a higher aluminum concentration than the second interlayer of the first graded transition body.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 13, 2018
From: BRIERE, MICHAEL A.
To: INTERNATIONAL RECTIFIER CORPORATION
Reel/Frame 044908/0225 →
MERGER AND CHANGE OF NAME Recorded Feb 13, 2018
From: INFINEON TECHNOLOGIES AMERICAS CORP.; INTERNATIONAL RECTIFIER CORPORATION
To: INFINEON TECHNOLOGIES AMERICAS CORP.
Reel/Frame 044908/0264 →
Continuity (4)
Division 14619942 · Feb 11, 2015
Division 13405180 · Feb 24, 2012
Provisional Application 61449046 · Mar 3, 2011
Related Publication 20180083106A1 · Mar 22, 2018