Resistance-based memory compiler

1. A non-transitory computer-readable storage medium storing instructions that, when executed by one or more processors of a computer system, cause the computer system to generate, based on user input, one or more netlist files for configuring a memory array by performing a number of operations comprising:

providing a memory block including a controller, a number of reference voltage generators, a number of sense amplifiers, and a number of memory columns each including a plurality of resistance-based memory (RBM) cells;

selecting the number of reference voltage generators to include in the memory block based on the user input;

selecting the number of sense amplifiers to include in the memory block based on the user input; and

determining how many of the sense amplifiers are to be coupled to each of the reference voltage generators based on the user input.

2. The non-transitory computer-readable storage medium of claim 1 , wherein execution of the instructions for determining how many of the sense amplifiers are to be coupled to each of the reference voltage generators causes the computer system to perform operations further comprising:

selecting, for a respective one of the reference voltage generators, a corresponding number of the memory columns to share the respective reference voltage generator.

3. The non-transitory computer-readable storage medium of claim 1 , wherein:

a first netlist file configuration provides a single reference voltage generator for all the sense amplifiers in the memory block;

a second netlist file configuration provides a different reference voltage generator for a selected number of the sense amplifiers in the memory block; and

a third netlist file configuration provides a dedicated reference voltage generator for each of the sense amplifiers in the memory block.

4. The non-transitory computer-readable storage medium of claim 1 , wherein execution of the instructions causes the computer system to perform operations further comprising:

providing a column bias circuit for the memory block;

selecting a number of programmable current sources to include in the column bias circuit based on the user input; and

determining how many of the memory columns are to be coupled to each of the programmable current sources based on the user input.

5. The non-transitory computer-readable storage medium of claim 4 , wherein:

a first netlist file configuration provides a single programmable current source for all the memory columns in the memory block;

a second netlist file configuration provides a different programmable current source for a selected number of the memory columns in the memory block; and

a third netlist file configuration provides a dedicated programmable current source for each of the memory columns in the memory block.

6. The non-transitory computer-readable storage medium of claim 1 , wherein execution of the instructions causes the computer system to perform operations further comprising:

providing a dual-purpose dummy track block in the memory block, the dual-purpose dummy track block including a number of columns each including a plurality of dummy RBM cells.

7. The non-transitory computer-readable storage medium of claim 6 , wherein the dual-purpose dummy track block is configured to determine timing information for read and write operations of the memory array.

8. The non-transitory computer-readable storage medium of claim 6 , wherein the dual-purpose dummy track block is configured to determine a course reference voltage for the memory array.

9. The non-transitory computer-readable storage medium of claim 6 , wherein a first of the plurality of dummy RBM cells in a selected column of the dual-purpose dummy track block comprises a first application specific bit cell coupled to be coupled to a first supply voltage, and a second of the plurality of dummy RBM cells in the selected column of the dual-purpose dummy track block comprises a second application specific bit cell coupled to be coupled to a second supply voltage different than the first voltage supply.

10. The non-transitory computer-readable storage medium of claim 9 , wherein the first application specific bit cell is configured to generate a first reference voltage, and the second application specific bit cell is configured to generate a second reference voltage different than the first reference voltage.

11. The non-transitory computer-readable storage medium of claim 10 , wherein the first and second reference voltages are configured to determine a logic state of a multi-valued RBM cell in the memory array.

12. The non-transitory computer-readable storage medium of claim 1 , wherein the controller is configured to adjust a write voltage for write operations based on a comparison between test data stored in a selected RBM cell and data read from the selected RBM cell.

13. The non-transitory computer-readable storage medium of claim 1 , wherein the controller is configured to adjust a reference voltage for read operations based on a comparison between test data stored in a selected RBM cell and known data.