Display device
A gate signal line driving circuit includes plural basic circuits, each outputting to a gate signal line a gate signal which is high during a high signal period and low during a low signal period. Each of the basic circuits includes: agate line high voltage application circuit which is turned on in accordance with the high signal period to apply the high voltage to the gate signal line; a gate line low voltage application circuit which is turned on in accordance with the low signal period t apply the low voltage to the gate signal line; and a second gate line low voltage application circuit which is turned on to apply the low voltage to the gate signal line in at least a part of a period between turning off the gate line high voltage application circuit and turning on the gate line low voltage application circuit.
1. A display device comprising:
a plurality of pixels arranged in a matrix;
a plurality of gate signal lines each applying a gate signal to the corresponding pixels; and
a gate signal line driving circuit outputting the gate signals to the plurality of gate signal lines,
wherein the gate signal line driving circuit comprises:
a plurality of shift register basic circuits each of which outputs to the corresponding gate signal line a gate signal which has a high voltage during a high signal period and has a low voltage during a low signal period; and
a first clock signal line applying a first clock signal to the gate signal line driving circuit,
wherein each of the shift register basic circuits comprises:
a first transistor which is in an ON state in accordance with the high signal period to apply the high voltage of the first clock signal to the corresponding gate signal line;
a second transistor which is in an ON state in accordance with the low signal period to apply the low voltage to the corresponding gate signal line;
a third transistor which is turned on to apply the low voltage to the corresponding gate signal line in at least a part of a period until the second transistor is turned on after the first transistor is turned off;
a fourth transistor which applies an OFF voltage to a control electrode of the second transistor in an ON state; and
a fifth transistor which applies an ON voltage to a control electrode of the second transistor in an ON state,
wherein a common ON control signal is supplied from a previous shift register basic circuit to both a control electrode of the fourth transistor and a control electrode of the first transistor,
wherein both the fourth transistor and the first transistor are turned on by the common ON control signal during the high signal period, and the control electrode of the fifth transistor is electrically connected to the first clock signal line, and
wherein the fifth transistor is turned on by the first clock signal.
2. The display device according to claim 1 , wherein a gate signal of a subsequent stage is input to a control electrode of the third transistor of each of the shift register basic circuits.
3. The display device according to claim 1 , wherein each of the shift register basic circuits further comprises a sixth transistor which applies an OFF voltage to a control electrode of the fourth transistor.