FinFET device and method of forming
A finFET device and a method of forming are provided. The device includes a transistor comprising a gate electrode and a first source/drain region next to the gate electrode, the gate electrode being disposed over a first substrate. The device also includes a first dielectric layer extending along the first source/drain region, and a second dielectric layer overlying the first dielectric layer. The device also includes a contact disposed in the first dielectric layer and in the second dielectric layer, the contact contacting the gate electrode and the first source/drain region. A first portion of the first dielectric layer extends between the contact and the gate electrode. The contact extends along a sidewall of the first portion of the first dielectric layer and a first surface of the first portion of the first dielectric layer, the first surface of the first portion being farthest from the first substrate.
1. A device, comprising:
a transistor comprising a gate electrode and a first source/drain region next to the gate electrode, the gate electrode being disposed over a first substrate;
a first dielectric layer extending along the first source/drain region;
a second dielectric layer overlying the first dielectric layer;
a contact disposed in the first dielectric layer and in the second dielectric layer, the contact contacting the gate electrode and the first source/drain region, wherein a first portion of the first dielectric layer extends between the contact and the gate electrode, and wherein the contact extends along a sidewall of the first portion of the first dielectric layer and a first surface of the first portion of the first dielectric layer, the first surface of the first portion being farthest from the first substrate.
2. The device according to claim 1 , wherein the sidewall is tapered.
3. The device according to claim 1 , wherein the second dielectric layer contacts a first surface of the gate electrode, and wherein the first surface of the gate electrode is substantially parallel to a major surface of the first substrate.
4. The device according to claim 1 , wherein a surface of the contact that is farthest from the first substrate is substantially planar with a major surface of the second dielectric layer that is farthest from the first substrate.
5. A device, comprising:
a transistor comprising a gate structure and a plurality of source/drain regions;
a first dielectric layer extending along the gate structure and the plurality of source/drain regions;
a second dielectric layer overlying the first dielectric layer;
an electrical connector disposed in the first dielectric layer and in the second dielectric layer, the electrical connector contacting the gate structure and a first source/drain region of the plurality of source/drain regions, wherein the first dielectric layer extends between a first interface and a second interface, the first interface being an interface of the electrical connector and the first source/drain region, and the second interface being an interface of the electrical connector and the gate structure, and wherein an angle formed by the second interface and a sidewall of a gate electrode of the gate structure is substantially perpendicular.
6. The device according to claim 5 , wherein a top surface of the gate structure is substantially planar with a top surface of the first dielectric layer.
7. The device according to claim 5 , wherein the electrical connector comprises one or more tapered sidewalls.
8. The device according to claim 5 , wherein a bottom surface of the electrical connector extends along a gate electrode, a gate dielectric layer, a gate spacer, and the first dielectric layer.
9. The device according to claim 5 , wherein a continuous sidewall of the electrical connector extends along the first dielectric layer and the second dielectric layer.
10. The device according to claim 5 , wherein the gate structure comprises a gate electrode, the electrical connector contacts and extends along a first portion of a first surface of the gate electrode, and the second dielectric layer contacts and extends along a second portion of the first surface of the gate electrode.
11. The device according to claim 5 , wherein the electrical connector comprises a barrier layer and a conductive material overlying the barrier layer.
12. The device according to claim 5 , wherein the electrical connector contacts and extends along a first portion of a first surface of the first source/drain region, and the first dielectric layer contacts and extends along a second portion of the first surface of the first source/drain region.
13. The device according to claim 12 , wherein a sidewall of the electrical connector extends in a substantially straight line between the first surface of the first source/drain region and a surface of the second dielectric layer that is furthest from the first source/drain region.
14. The device according to claim 12 , wherein the second portion of the first surface of the first source/drain region is further from the gate structure than the first interface.
15. The device according to claim 12 , wherein the second portion of the first surface of the first source/drain region is closer to the gate structure than the first interface.
16. The device according to claim 12 , wherein a thickness of the electrical connector in the second dielectric layer is greater than a thickness of the electrical connector in the first dielectric layer.
17. A device, comprising:
a transistor comprising a gate structure and a plurality of source/drain regions;
a plurality of dielectric layers overlying the transistor;
an electrical connector extending through the plurality of dielectric layers, the electrical connector contacting a gate electrode of the gate structure and a first source/drain region of the plurality of source/drain regions, wherein a first portion of the plurality of dielectric layers extends between the electrical connector and the gate structure, and between the first source/drain region and the gate structure, wherein the first portion of the plurality of dielectric layers contacts the electrical connector on a first surface of the first portion and a second surface of the first portion, the first surface of the first portion being non-planar with the second surface of the first portion, and wherein a shape of the first portion, in a cross-sectional view, is defined by the gate structure, the first source/drain region, and the electrical connector.
18. The device according to claim 17 , wherein a first surface of the first portion of the plurality of dielectric layers is planar with a surface of the gate electrode.
19. The device according to claim 17 , wherein the electrical connector contacts a first surface of the first source/drain region, the first portion of the plurality of dielectric layers contacts the first surface of the first source/drain region, and a second portion of the plurality of dielectric layers contacts the first surface of the first source/drain region, wherein the first portion of the plurality of dielectric layers is separated from the second portion of the plurality of dielectric layers by a portion of the electrical connector.
20. The device according to claim 17 , wherein a surface of the electrical connector that contacts the first source/drain region has a dimension that is greater than a surface of the electrical connector that is farthest from the first source/drain region.