IP Library › Granted Patent US 10,339,015
Granted Patent B2
US 10,339,015 · App. 15/832,251 · Granted Jul 2, 2019

Maintaining system reliability in a CPU with co-processors

Inventors: Pradip Bose (Yorktown Heights, NY); Alper Buyuktosunoglu (White Plains, NY); Jingwen Leng (Yorktown Heights, NY); Ramon Bertran Monfort (Bronx, NY)
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
G06F11/1658G06F11/1629G06F2201/805G06F2201/82
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Quick Facts
Patent No.
US 10,339,015
App. No.
15/832,251
Granted
Jul 2, 2019
Kind
B2
Abstract

A computer-implemented method is provided that is performed in a computer having a processor and multiple co-processors. The method includes launching a same set of operations in each of an original co-processor and a redundant co-processor, from among the multiple co-processors, to obtain respective execution signatures from the original co-processor and the redundant co-processor. The method further includes detecting an error in an execution of the set of operations by the original co-processor, by comparing the respective execution signatures. The method also includes designating the execution of the set of operations by the original co-processor as error-free and committing a result of the execution, responsive to identifying a match between the respective execution signatures. The method additionally includes performing an error recovery operation that replays the set of operations by the original co-processor and the redundant co-processor, responsive to identifying a mismatch between the respective execution signatures.

Claims (18)

1. A computer program product for maintaining reliability of a computer having a Central Processing Unit (CPU) and multiple co-processors, the computer program product comprising a non-transitory computer readable storage medium having program instructions embodied therewith, the program instructions executable by a computer to cause the computer to perform a method comprising:

launching a same set of operations in each of an original co-processor and a redundant co-processor, from among the multiple co-processors, to obtain respective execution signatures from the original co-processor and the redundant co-processor;

detecting an error in an execution of the set of operations by the original co-processor, by comparing the respective execution signatures;

designating the execution of the set of operations by the original co-processor as error-free and committing a result of the execution, responsive to identifying a match between the respective execution signatures; and

performing an error recovery operation that replays the set of operations by the original co-processor and the redundant co-processor, responsive to identifying a mismatch between the respective execution signatures.

2. The computer program product of claim 1 , wherein a unit of targeted acceleration is at a kernel-level granularity with respect to a complete application.

3. The computer program product of claim 1 , wherein the set of operations executed by the redundant co-processor is a shadow copy of kernel code executed by the original co-processor.

4. The computer program product of claim 3 , wherein the shadow copy executed by the redundant co-processor uses a same complete set of input data as the kernel code executed by the original co-processor.

5. The computer program product of claim 1 , wherein the respective execution signatures are directed to a specific execution state within a launched kernel.

6. A computer processing system, comprising:

a Central Processing Unit (CPU);

multiple co-processors operably coupled to the CPU; and

a runtime system, configured to:

launch a same set of operations in each of an original co-processor and a redundant co-processor, from among the multiple co-processors, to obtain respective execution signatures from the original co-processor and the redundant co-processor;

detect an error in an execution of the set of operations by the original co-processor, by comparing the respective execution signatures;

designate the execution of the set of operations by the original co-processor as error-free and committing a result of the execution, responsive to identifying a match between the respective execution signatures; and

perform an error recovery operation that replays the set of operations by the original co-processor and the redundant co-processor, responsive to identifying a mismatch between the respective execution signatures.

7. The computer processing system of claim 6 , wherein the computer processing system is comprised in a single node of a multi-computer processing system, and wherein the runtime system is further configured to prevent the error from propagating to other nodes in the multi-node computing system.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 5, 2017
From: BOSE, PRADIP; BUYUKTOSUNOGLU, ALPER; LENG, JINGWEN; BERTRAN MONFORT, RAMON
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 044303/0199 →
Continuity (2)
Continuation 15459788 · Mar 15, 2017
Related Publication 20180267868A1 · Sep 20, 2018