IP Library Granted Patent US 10,242,985
Granted Patent B2
US 10,242,985 · App. 15/835,133 · Granted Mar 26, 2019

Semiconductor device comprising a standard cell and a non-active transistor

Inventor: Hiroyuki Shimbo (Kyoto, JP)
Assignee: Socionext Inc.
H01L27/0924H01L27/0207H01L27/0629H01L27/0676H01L27/0886H01L29/6681
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Quick Facts
Patent No.
US 10,242,985
App. No.
15/835,133
Granted
Mar 26, 2019
Kind
B2
Abstract

Disclosed herein is a semiconductor device including two standard cells which are arranged adjacent to each other in an X direction. One of the two standard cells includes a plurality of first fins which extend in the X direction, and which are arranged along a boundary between the two standard cells in a Y direction. The other standard cell includes a plurality of second fins which extend in the X direction, and which are arranged along the boundary between the two standard cells in the Y direction. The plurality of second fins includes a dummy fin.

Claims (22)

1. A semiconductor device comprising first and second standard cells which are arranged adjacent to each other in a first direction, wherein

the first standard cell includes a plurality of first fins which extend in the first direction, and which are arranged along a boundary between the first and second standard cells in a second direction that is perpendicular to the first direction,

the second standard cell includes a plurality of fin transistors, fins of the plurality of fin transistors extend in the first direction and are arranged in the second direction along the boundary between the first and second standard cells such that each of the fins of the plurality of fin transistors is aligned with an associated one of the plurality of first fins,

the second standard cell further includes at least one first active transistor different from the plurality of fin transistors, and

at least one of the plurality of fin transistors is at least one non-active transistor which does not contribute to any logical function of the second standard cell.

2. The semiconductor device of claim 1 , wherein all of the plurality of fin transistors are non-active transistors.

3. The semiconductor device of claim 1 , wherein the plurality of fin transistors include a second active transistor different from the at least one non-active transistor.

4. The semiconductor device of claim 3 , wherein a fin of the second active transistor extends in the first direction from one end portion to the other end portion of the second standard cell.

5. The semiconductor device of claim 1 , wherein at least one of the first fins is a fin of a third active transistor.

6. The semiconductor device of claim 5 , wherein all of the first fins are fins of active transistors including the third active transistor.

7. The semiconductor device of claim 6 , wherein the fin of the third active transistor extends in the first direction from one end portion to the other end portion of the first standard cell.

8. A semiconductor device comprising first and second standard cells which are arranged adjacent to each other in a first direction, wherein

the first standard cell includes a plurality of first fins which extend in the first direction, and which are arranged along a boundary between the first and second standard cells in a second direction that is perpendicular to the first direction,

the second standard cell includes a plurality of fin transistors, fins of the plurality of fin transistors extend in the first direction and are arranged in the second direction along the boundary between the first and second standard cells such that each of the fins of the plurality of fin transistors is aligned with an associated one of the plurality of first fins,

the second standard cell further includes at least one active transistor different from the plurality of fin transistors, and

at least one of the plurality of fin transistors is at least one OFF-state transistor, a fin and a gate line of the at least one OFF-state transistor are connected to a power supply line.

9. The semiconductor device of claim 8 , wherein all of the plurality of fin transistors are OFF-state transistors.

10. The semiconductor device of claim 8 , wherein the plurality of fin transistors include a second active transistor different from the at least one OFF-state transistor.

11. The semiconductor device of claim 10 , wherein a fin of the second active transistor extends in the first direction from one end portion to the other end portion of the second standard cell.

12. The semiconductor device of claim 8 , wherein at least one of first fins is a fin of a third active transistor.

13. The semiconductor device of claim 12 , wherein all of the first fins are fins of active transistors including the third active transistor.

14. The semiconductor device of claim 13 , wherein the fin of the third active transistor extends in the first direction from one end portion to the other end portion of the first standard cell.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 7, 2017
From: SHIMBO, HIROYUKI
To: SOCIONEXT, INC.
Reel/Frame 044333/0619 →
Priority Claims (1)
JP 2013-183350 · Sep 4, 2013 · national
Continuity (3)
Continuation 15059974
Continuation PCTJP2014002206 · Apr 18, 2014
Related Publication 20180097004A1 · Apr 5, 2018
Cited By (1)
US 12,494,430