Galois field pipelined multiplier with polynomial and beta input passing scheme
The disclosure provides a very flexible mechanism for a storage controller to create RAID stripes and to re-create corrupted stripes when necessary using the erasure coding scheme. Typically, this is known as a RAID 6 implementation/feature. The erasure code calculations are generated using the Galois Multiplication hardware and the system controller can pass any polynomial into the hardware on a per stripe calculation basis. The polynomial value is passed to the hardware via an input descriptor field. The descriptor controls the entire computation process.
1. A system for performing a computation on a multiplier, comprising:
a load pointer to direct a 8-bit data in bus to a correct multiplier block of a series of multipliers in a round robin fashion;
the series of multipliers adapted to produce a series of 8 bit results, wherein the correct multiplier block is adapted to produce an individual 8 bit multiplier result based on the 8-bit data in bus; and
a result pointer that selects the individual 8 bit multiplier result from the correct multiplier block result for presentation on an output bus.
2. The system of claim 1 , wherein the series of multipliers includes a plurality of multipliers in parallel with each other.
3. The system of claim 1 , wherein the series of multipliers use a polynomial select value and a beta value.
4. The system of claim 3 , wherein the system is adapted to receive a descriptor.
5. The system of claim 4 , wherein the descriptor includes a polynomial select value and a beta value.
6. The system of claim 5 , wherein the beta value define an 8-bit constant value to be multiplied by the 8-bit data.
7. The system of claim 6 , wherein the descriptor includes a source of the 8-bit data.
8. The system of claim 7 , wherein the descriptor includes a P buffer.
9. The system of claim 8 , wherein the descriptor includes a Q buffer.
10. The system of claim 1 , wherein the series of multipliers is a Galois Field multiplier.
11. The system of claim 10 , wherein the series of multipliers uses a Linear Feedback Shift Register.
12. The system of claim 11 , wherein the series of multipliers are implemented in a 9 instance deep×32 instance wide arrangement.
13. The system of claim 1 , wherein the system resides in an IRAY node.