IP Library Granted Patent US 10,277,048
Granted Patent B2
US 10,277,048 · App. 15/838,026 · Granted Apr 30, 2019

Half bridge power conversion circuits using GaN devices

Inventors: Daniel Marvin Kinzer (El Segundo, CA); Santosh Sharma (Laguna Niguel, CA); Ju Zhang (Monterey Park, CA)
Assignee: Navitas Semiconductor, Inc.
H02J7/0052H01L23/49503H01L23/49562H01L23/49575H01L23/528H01L25/072H01L27/0248H01L27/088H01L27/0883H01L29/1033H01L29/2003H01L29/402H01L29/41758H02M1/088H02M3/157H02M3/1584H02M3/1588H03K3/012H03K3/356017H03K17/102H03K19/018507H01L2924/00H01L2924/0002H02M3/155H02M2001/0048Y02B70/1466Y02B70/1483
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Quick Facts
Patent No.
US 10,277,048
App. No.
15/838,026
Granted
Apr 30, 2019
Kind
B2
Abstract

GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions. Some devices employ electro-static discharge circuits and features formed within the GaN-based devices to improve the reliability and performance of the half bridge power conversion circuits.

Claims (28)

1. A half-bridge circuit comprising:

a low side circuit disposed on a first semiconductor die, and including a GaN-based low side switch and a GaN-based level shift circuit; and

a high side circuit disposed on a second semiconductor die, and including a GaN-based high side switch that is coupled to and controlled by the GaN-based level shift circuit.

2. The half-bridge circuit of claim 1 wherein the GaN-based level shift circuit receives an input signal at a first voltage and generates an output signal at a second voltage, wherein the second voltage is higher than the first voltage and the second voltage controls the GaN-based high side switch.

3. The half-bridge circuit of claim 2 wherein the second voltage is at least 20 volts greater than the first voltage.

4. The half-bridge circuit of claim 1 wherein the GaN-based level shift circuit includes an enhancement mode GaN transistor.

5. The half-bridge circuit of claim 1 wherein the high side circuit includes a level shift receiver circuit that receives a control signal from the GaN-based level shift circuit and in response controls a high side switch driver circuit that operates the GaN-based high side switch.

6. A half-bridge circuit comprising:

a high side GaN-based switch coupled between a voltage source and a switch-node;

a low side GaN-based switch coupled between the switch-node and a ground; and

a GaN-based level shift circuit coupled to the high side GaN-based switch and configured to receive an input signal, level shift the input signal from a first voltage to a second voltage and transmit an output signal at the second voltage to a circuit that controls the high side GaN-based switch,

wherein the high side GaN-based switch is disposed on a first monolithic die and the low side GaN-based switch is disposed on a second monolithic die, and

wherein the GaN-based level shift circuit is disposed on the second monolithic die and is configured to transmit the output signal from the second monolithic die to the first monolithic die.

7. The half-bridge circuit of claim 6 wherein the first monolithic die includes a receiver circuit that receives the output signal and in response controls a high side switch driver circuit that operates the high side GaN-based switch.

8. The half-bridge circuit of claim 6 wherein the second voltage is higher than the first voltage.

9. The half-bridge circuit of claim 8 wherein the second voltage is at least 20 volts higher than the first voltage.

10. The half-bridge circuit of claim 6 wherein the GaN-based level shift circuit includes an enhancement mode GaN transistor.

11. A power conversion circuit comprising:

a first semiconductor device including a first GaN-based switch coupled between a voltage source and a switch-node; and

a second semiconductor device including a second GaN-based switch coupled between the switch-node and a ground, and further including a GaN-based level shift circuit coupled to and configured to control the first GaN-based switch,

wherein the first semiconductor device is disposed on a first die and the second semiconductor device is disposed on a second die.

12. The power conversion circuit of claim 11 wherein the level shift circuit is configured to send a level shift signal from the second semiconductor device to the first semiconductor device.

13. The power conversion circuit of claim 12 wherein the first semiconductor device includes a receiver circuit that receives the level shift signal and in response sends a control signal to a first driver circuit that controls the first GaN-based switch.

14. The power conversion circuit of claim 12 wherein the level shift circuit receives a signal at a first voltage and in response sends the level shift signal to the first semiconductor device at a second voltage.

15. The power conversion circuit of claim 14 wherein the second voltage is higher than the first voltage.

16. The power conversion circuit of claim 14 wherein the second voltage is at least 20 volts higher than the first voltage.

17. The power conversion circuit of claim 11 wherein the level shift circuit includes an enhancement mode GaN transistor.

18. The power conversion circuit of claim 11 wherein the level shift circuit includes an inverter having a resistor pull up and a pull down transistor.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNMENT DOCUMENTS AND THE RECEIVING PARTY'S POSTAL CODE PREVIOUSLY RECORDED AT REEL: 053864 FRAME: 0208. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 9, 2021
From: NAVITAS SEMICONDUCTOR, INC.
To: NAVITAS SEMICONDUCTOR LIMITED
Reel/Frame 056758/0314 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 23, 2020
From: NAVITAS SEMICONDUCTOR, INC.
To: NAVITAS SEMICONDUCTOR LIMITED
Reel/Frame 053864/0208 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 22, 2019
From: KINZER, DANIEL MARVIN; SHARMA, SANTOSH; ZHANG, JU
To: NAVITAS SEMICONDUCTOR, INC.
Reel/Frame 048082/0840 →
Continuity (4)
Continuation 14667319 · Mar 24, 2015
Provisional Application 62051160 · Sep 16, 2014
Provisional Application 62127725 · Mar 3, 2015
Related Publication 20180102661A1 · Apr 12, 2018