Process isolation for out of process page fault handling

1. A method comprising:

detecting, by a processing device, a hardware event;

determining a first virtual memory address associated with the hardware event, wherein the first virtual memory address is associated with a first processing thread;

identifying, using the first virtual memory address, an entry of a logical address table, the entry comprising a file descriptor and a file offset associated with a file;

identifying a memory address table associated with the file descriptor;

translating, using the memory address table, the file offset into a second virtual memory address associated with a second processing thread; and

transmitting, to the second processing thread, a notification comprising the second virtual memory address.

2. The method of claim 1 , wherein the hardware event comprises a page fault generated by the first processing thread executing an instruction associated with the first virtual memory address.

3. The method of claim 1 , further comprising:

registering, with a kernel, the second processing thread to receive notifications of hardware events generated by the first processing thread.

4. The method of claim 1 , wherein the memory address table is a component of a kernel executed by the processing device.

5. The method of claim 1 , wherein the first processing thread is associated with a first virtual machine and the second processing thread is associated with a second virtual machine.

6. The method of claim 1 , wherein the file comprises a memory-mapped file object of one of a non-volatile file system or a volatile file system.

7. The method of claim 1 further comprising:

responsive to receiving, by a kernel, a request from the second processing thread, retrieving data from an auxiliary storage and populating the data at the first virtual memory address.

8. The method of claim 7 , further comprising:

identifying a third processing thread associated with the first virtual memory address; and

waking up the third processing thread.

9. A system comprising:

a memory;

a processing device executing a kernel and operatively coupled to the memory, the processing device to:

detect a hardware event;

determine a first virtual memory address associated with the hardware event, wherein the first virtual memory address is associated with a first processing thread;

identify, using the first virtual memory address, an entry of a logical address table, the entry comprising a file descriptor and a file offset associated with a file;

identify a memory address table associated with the file descriptor;

translate, using the memory address table, the file offset into a second virtual memory address associated with a second processing thread; and

transmit, to the second processing thread, a notification comprising the second virtual memory address.

10. The system of claim 9 , wherein the hardware event comprises a page fault generated by the first processing thread executing an instruction associated with the first virtual memory address.

11. The system of claim 9 , wherein the processing device is further to register, with a kernel, the second processing thread to receive notifications of hardware events generated by the first processing thread.

12. The system of claim 9 , wherein the memory address table is a component of a kernel executed by the processing device.

13. The system of claim 9 , wherein the first processing thread is associated with a first virtual machine and the second processing thread is associated with a second virtual machine.

14. The system of claim 9 , wherein the file comprises a memory-mapped file object of one of a non-volatile file system or a volatile file system.

15. The system of claim 9 , wherein the processing device is further to:

responsive to receiving, by a kernel, a request from the second processing thread, retrieve data from an auxiliary storage and populating the data at the first virtual memory address;

identify a third processing thread associated with the first virtual memory address; and

wake up the third processing thread.

16. A non-transitory machine-readable storage medium storing instructions that, when executed, cause a processing device to:

detect, by the processing device, a hardware event;

determine a first virtual memory address associated with the hardware event, wherein the first virtual memory address is associated with a first processing thread;

detect, by a kernel, a hardware event corresponding to a first virtual memory address associated with a first processing thread;

identify, using the first virtual memory address, an entry of a logical address table, the entry comprising a file descriptor and a file offset associated with a file;

identify a memory address table associated with the file descriptor;

translate, using the memory address table, the file offset into a second virtual memory address associated with a second processing thread; and

transmit, to the second processing thread, a notification comprising the second virtual memory address.

17. The non-transitory machine-readable storage medium of claim 16 , wherein the hardware event comprises a page fault generated by the first processing thread executing an instruction associated with the first virtual memory address.

18. The non-transitory machine-readable storage medium of claim 16 , wherein the processing device is further to register, with a kernel, the second processing thread to receive notifications of hardware events generated by the first processing thread.

19. The non-transitory machine-readable storage medium of claim 16 , wherein the memory address table is a component of a kernel executed by the processing device.

20. The non-transitory machine-readable storage medium of claim 16 , wherein the first processing thread is associated with a first virtual machine and the second processing thread is associated with a second virtual machine.