IP Library Granted Patent US 10,332,887
Granted Patent B2
US 10,332,887 · App. 15/841,257 · Granted Jun 25, 2019

Buried word line of a dynamic random access memory and method for fabricating the same

Inventors: Feng-Yi Chang (Tainan, TW); Chun-Hsien Lin (Tainan, TW); Fu-Che Lee (Taichung, TW)
Assignees: UNITED MICROELECTRONICS CORP.; Fujian Jinhua Integrated Circuit Co., Ltd.
H01L27/10823H01L27/10876H01L29/4991H01L21/0214H01L29/0657H01L29/4236H01L29/518
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Quick Facts
Patent No.
US 10,332,887
App. No.
15/841,257
Granted
Jun 25, 2019
Kind
B2
Abstract

A method for fabricating a buried word line (BWL) of a dynamic random access memory (DRAM) includes the steps of: forming a first doped region in a substrate; removing part of the first doped region to form a trench in the substrate; forming a gate structure in the trench; and forming a barrier structure between the gate structure and the first doped region.

Claims (12)

1. A buried word line (BWL) of a dynamic random access memory (DRAM), comprising:

a trench in a substrate;

a doped region adjacent to two sides of the trench;

a gate structure in the trench, wherein the gate structure comprises:

a conductive layer in the trench;

a gate dielectric layer between the conductive layer and the substrate; and

a barrier structure between the gate structure and the doped region, wherein a topmost surface of the barrier structure is even with a topmost surface of the gate dielectric layer and the barrier structure and the gate dielectric layer comprise different heights.

2. The buried word line (BWL) of a dynamic random access memory (DRAM) of claim 1 , wherein a top surface of the barrier structure is higher than a bottom surface of the doped region and a bottom surface of the barrier structure is even with the bottom surface of the doped region.

3. The buried word line (BWL) of a dynamic random access memory (DRAM) of claim 1 , wherein a top surface of the barrier structure is higher than a bottom surface of the doped region and a bottom surface of the barrier structure is lower than the bottom surface of the doped region.

4. The buried word line (BWL) of a dynamic random access memory (DRAM) of claim 1 , wherein the barrier structure and the gate dielectric layer comprise same material.

5. The buried word line (BWL) of a dynamic random access memory (DRAM) of claim 1 , further comprising a hard mask on the gate structure.

6. The buried word line (BWL) of a dynamic random access memory (DRAM) of claim 1 , further comprising an air gap in the conductive layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 13, 2017
From: CHANG, FENG-YI; LIN, CHUN-HSIEN; LEE, FU-CHE
To: UNITED MICROELECTRONICS CORP.; FUJIAN JINHUA INTEGRATED CIRCUIT CO., LTD.
Reel/Frame 044391/0516 →
Priority Claims (1)
CN 2017 1 1146632 · Nov 17, 2017 · national
Continuity (1)
Related Publication 20190157274A1 · May 23, 2019