Non-volatile memory using a reduced number of interconnect terminals
A first signal may be received from a memory device at a first interconnect terminal of a number of interconnect terminals via a serial communication interface that indicates the memory device includes a NAND type memory device. Whether a second signal that indicates the NAND type memory device is initialized has been received from the memory device at a second interconnect terminal of the number of interconnect terminals may be determined. An operation associated with the NAND type memory device may be performed at the second interconnect terminal and a third interconnect terminal in response to determining the second signal has been received from the memory device indicating the NAND type memory device is initialized.
1. A processing device comprising:
a hardware logic circuit to implement a hardware state machine; and
a plurality of interconnect terminals coupled to the hardware logic circuit, the hardware logic circuit to:
receive, from a memory device at a first interconnect terminal of the plurality of interconnect terminals via a serial communication interface, a first signal indicating the memory device is a NAND type memory device;
determine whether a second signal has been received from the memory device at a second interconnect terminal of the plurality of interconnect terminals, the second signal indicating the NAND type memory device is initialized; and
in response to determining the second signal has been received from the memory device indicating the NAND type memory device is initialized, perform an operation associated with the NAND type memory device at the second interconnect terminal and a third interconnect terminal of the plurality of interconnect terminals.
2. The processing device of claim 1 , further comprising a clock generation circuit coupled to a fourth interconnect terminal of the plurality of interconnect terminals, the clock generation circuit to generate a timing signal to be provided to the memory device at the fourth interconnect terminal of the plurality of interconnect terminals.
3. The processing device of claim 1 , wherein the operation is a read operation, wherein the hardware logic circuit for the read operation is to:
transmit a first read control signal to the NAND type memory device at the second interconnect terminal and the third interconnect terminal;
receive a second read control signal from the NAND type memory device at the second interconnect terminal that indicates the NAND type memory device is ready to provide data associated with the read operation; and
receive the data associated with the read operation from the NAND type memory device at the second interconnect terminal and the third interconnect terminal.
4. The processing device of claim 1 , wherein the operation is a write operation, wherein the hardware logic circuit for the write operation is to:
transmit a first write control signal to the NAND type memory device at the second interconnect terminal and the third interconnect terminal;
receive a second write control signal from the NAND type memory device at the second interconnect terminal that indicates the NAND type memory device is ready to receive data associated with the write operation; and
provide the data associated with the write operation to the NAND type memory device at the second interconnect terminal and the third interconnect terminal.
5. The processing device of claim 1 , further comprising:
a sample and hold circuit to measure values associated with signals received at the plurality of interconnect terminals, hold the values associated with the signals and produce an output corresponding to the values; and
a data buffer operatively coupled to the sample and hold circuit, the data buffer to store the output corresponding to the values.
6. The processing device of claim 1 , wherein the hardware logic circuit is further to:
receive, from the memory device at the second interconnect terminal of the plurality of interconnect terminals, a third signal indicating the NAND type memory device is not initialized.
7. The processing device of claim 1 , wherein the plurality of interconnect terminals is less than seven interconnect terminals.
8. A system comprising:
a processing device comprising a plurality of interconnect terminals; and
a memory device comprising a NAND type memory device operatively coupled to the processing device at the plurality of interconnect terminals via a serial communication interface, wherein the NAND type memory device is to transmit signals to the processing device via the plurality of interconnect terminals, the processing device to:
receive a first signal at a first interconnect terminal of the plurality of interconnect terminals;
determine that the memory device comprises the NAND type memory device based on the first signal;
receive a second signal at a second interconnect terminal of the plurality of interconnect terminals;
determine the NAND type memory device is initialized based on the second signal; and
perform an operation associated with the NAND type memory device at the second interconnect terminal and a third interconnect terminal of the plurality of interconnect terminals.
9. The system of claim 8 , wherein the second interconnect terminal of the plurality of interconnect terminals comprises a dual-purpose input output terminal.
10. The system of claim 8 , wherein the third interconnect terminal of the plurality of interconnect terminals comprises an input output terminal to provide or receive a signal from the memory device.
11. The system of claim 8 , further comprising:
a hardware state machine to monitor signals transmitted at the plurality of interconnect terminals from the memory device.
12. The system of claim 8 , wherein the operation is a read operation, wherein the processing device is to:
transmit a first read control signal to the NAND type memory device at the second interconnect terminal and the third interconnect terminal;
receive a second read control signal from the NAND type memory device at the second interconnect terminal that indicates the NAND type memory device is ready to provide data associated with the read operation; and
receive the data associated with the read operation from the NAND type memory device at the second interconnect terminal and the third interconnect terminal.
13. The system of claim 8 , wherein the operation is a write operation, wherein the processing device is to:
transmit a first write control signal to the NAND type memory device at the second interconnect terminal and the third interconnect terminal;
receive a second write control signal from the NAND type memory device at the second interconnect terminal that indicates the NAND type memory device is ready to receive data associated with the write operation; and
provide the data associated with the write operation to the NAND type memory device at the second interconnect terminal and the third interconnect terminal.
14. The system of claim 8 , further comprising:
a clock generation circuit coupled to a fourth interconnect terminal of the plurality of interconnect terminals, the clock generation circuit to generate a timing signal to be provided to the memory device at a fourth interconnect terminal of the plurality of interconnect terminals.
15. A method comprising:
receiving, from a memory device at a first interconnect terminal of a plurality of interconnect terminals via a serial communication interface, a first signal indicating the memory device comprises a NAND type memory device;
determining, by a processing device, whether a second signal has been received from the memory device at a second interconnect terminal of the plurality of interconnect terminals, the second signal indicating the NAND type memory device is initialized; and
in response to determining the second signal has been received from the memory device indicating the NAND type memory device is initialized, performing an operation associated with the NAND type memory device at the second interconnect terminal and a third interconnect terminal of the plurality of interconnect terminals.
16. The method of claim 15 , wherein the operation is a read operation comprising:
transmitting a first read control signal to the NAND type memory device at the second interconnect terminal and the third interconnect terminal;
receiving a second read control signal from the NAND type memory device at the second interconnect terminal that indicates the NAND type memory device is ready to provide data associated with the read operation; and
receiving the data associated with the read operation from the NAND type memory device at the second interconnect terminal and the third interconnect terminal.
17. The method of claim 15 , wherein the operation is a write operation comprising:
transmitting a first write control signal to the NAND type memory device at the second interconnect terminal and the third interconnect terminal;
receiving a second write control signal from the NAND type memory device at the second interconnect terminal that indicates the NAND type memory device is ready to receive data associated with the write operation; and
providing the data associated with the write operation to the NAND type memory device at the second interconnect terminal and the third interconnect terminal.
18. The method of claim 15 , further comprising:
receiving a third signal from the memory device at the second interconnect terminal indicating the operation associated with the NAND type memory device has been performed.
19. The method of claim 15 , further comprising:
receiving, from the memory device at the second interconnect terminal of the plurality of interconnect terminals, a third signal indicating the NAND type memory device is not initialized.
20. The method of claim 15 , wherein the plurality of interconnect terminals is less than seven interconnect terminals.