Perfectly symmetric gate-all-around FET on suspended nanowire
A semiconductor device including a plurality of suspended nanowires and a gate structure that is present on a channel region portion of the plurality of suspended nanowires. The gate structure includes a uniform length extending from an upper surface of the gate structure to the base of the gate structure. A dielectric spacer having a graded composition is present in direct contact with the gate structure. The dielectric spacer having a uniform length extending from an upper surface of the gate structure to the base of the gate structure. Source and drain regions are present on source and drain region portions of the plurality of suspended nanowires.
1. A method of forming as semiconductor device comprising:
forming a first replacement gate structure of light sensitive material is present on a channel region portion of the stack of suspended nanowires;
replacing the first replacement gate structure of the light sensitive material with a second replacement gate structure of a semiconductor gate material;
applying a surface treatment process to at least sidewall surfaces of the second replacement gate structure to convert a portion of the semiconductor gate material to a dielectric spacer on said at least the sidewall surfaces of the second replacement gate structure; and
replacing the second replacement gate structure with a functional gate structure.
2. The method of claim 1 , wherein the stack of nanowires is formed by a method comprising:
depositing alternating layers of nanowire semiconductor material and sacrificial material;
etching a first portion of the sacrificial material selectively to the nanowire semiconductor material, wherein a second portion of the sacrificial material remains to provide anchors; and
depositing a conformal dielectric layer on the exposed portions of the nanowire semiconductor material to provide a dielectric coating.
3. The method of claim 1 , wherein the first replacement gate structure of the light sensitive material is formed by a method that includes patterning a light sensitive material using lithography and development to provide the first replacement gate structure of the light sensitive material on the channel region portion of the stack of suspended nanowires.
4. The method of claim 3 , wherein the light sensitive material is comprised of a photoresist material selected from the group consisting of Hydrogen silsesquioxane (HSQ), Poly(methyl methacrylate) (PMMA), Poly(methyl glutarimide) (PMGI), Phenol formaldehyde resin (DNQ/Novolac), SU-8 and combinations thereof.
5. The method of claim 1 , wherein the replacing of the first replacement gate structure of the light sensitive material with the second replacement gate structure of the semiconductor gate material comprises:
forming a semiconductor source and drain replacement material on the exposed portions of the stack of suspended nanowires;
removing the first replacement gate structure to provide a gate opening to the channel region portion of the stack of suspended nanowires;
forming the second replacement gate structure of the semiconductor gate material in the gate opening to the channel region portion of the stack of suspended nanowires; and
removing the semiconductor source and drain replacement material.
6. The method of claim 5 , wherein the forming of the semiconductor source and drain replacement material on exposed portions of the stack of suspended nanowires comprises deposition of semiconductor material selected from the group consisting of germanium, silicon germanium, polysilicon germanium and combinations thereof.
7. The method of claim 1 , wherein the forming of the second replacement gate structure of the semiconductor gate material in the opening to the channel region portion of the stack of suspended nanowires comprises deposition of a semiconductor material having a composition selected from the group consisting of monocrystalline silicon, polysilicon and combinations thereof, or deposition of an oxide.
8. The method of claim 1 , wherein the applying the surface treatment process to said at least said sidewall surfaces of the second gate structure to convert the portion of the semiconductor gate material to the dielectric spacer on said at least the sidewall surfaces of the second gate structure comprises nitridation, ion implantation, plasma treatments, annealing, and a combination thereof.
9. The method of claim 8 , wherein the reacting the surface treatment process converts said sidewall portion and said upper portion of the second gate structure to a dielectric material, wherein the upper portion of the second gate structure that is converted to the dielectric material is removed by planarization.
10. The method of claim 2 , wherein the replacing of the second replacement gate structure with the functional gate structure comprises:
removing the dielectric coating from exposed portions of the suspended stack that are not covered with the second replacement gate structure;
forming an epitaxial source and drain region semiconductor material on the exposed portions of the suspended stack that are not covered with the second replacement gate structure;
diffusing dopant from the source and drain epitaxial semiconductor material to form source and drain extension regions in the exposed portions of the stack of suspended nanowires;
removing the second replacement gate structure with an etch process; and
forming the functional gate structure in the opening to the channel region portion of the stack of suspended nanowires.
11. A method of forming as semiconductor device comprising:
forming a first replacement gate structure of light sensitive material is present on a channel region portion of the stack of suspended nanowires;
replacing the first replacement gate structure of the light sensitive material with a second replacement gate structure of a semiconductor gate material;
applying a surface treatment process to at least sidewall surfaces of the second replacement gate structure to convert a portion of the semiconductor gate material to a dielectric spacer on said at least the sidewall surfaces of the second replacement gate structure, the dielectric spacer having a graded composition and a uniform length; and
replacing the second replacement gate structure with a functional gate structure.
12. The method of claim 11 , wherein the stack of nanowires is formed by a method comprising:
depositing alternating layers of nanowire semiconductor material and sacrificial material;
etching a first portion of the sacrificial material selectively to the nanowire semiconductor material, wherein a second portion of the sacrificial material remains to provide anchors; and
depositing a conformal dielectric layer on the exposed portions of the nanowire semiconductor material to provide a dielectric coating.
13. The method of claim 11 , wherein the first replacement gate structure of the light sensitive material is formed by a method that includes patterning a light sensitive material using lithography and development to provide the first replacement gate structure of the light sensitive material on the channel region portion of the stack of suspended nanowires.
14. The method of claim 13 , wherein the light sensitive material is comprised of a photoresist material selected from the group consisting of Hydrogen silsesquioxane (HSQ), Poly(methyl methacrylate) (PMMA), Poly(methyl glutarimide) (PMGI), Phenol formaldehyde resin (DNQ/Novolac), SU-8 and combinations thereof.
15. The method of claim 11 , wherein the replacing of the first replacement gate structure of the light sensitive material with the second replacement gate structure of the semiconductor gate material comprises:
forming a semiconductor source and drain replacement material on the exposed portions of the stack of suspended nanowires;
removing the first replacement gate structure to provide a gate opening to the channel region portion of the stack of suspended nanowires;
forming the second replacement gate structure of the semiconductor gate material in the gate opening to the channel region portion of the stack of suspended nanowires; and
removing the semiconductor source and drain replacement material.
16. The method of claim 15 , wherein the forming of the semiconductor source and drain replacement material on exposed portions of the stack of suspended nanowires comprises deposition of semiconductor material selected from the group consisting of germanium, silicon germanium, polysilicon germanium and combinations thereof.
17. The method of claim 11 , wherein the forming of the second replacement gate structure of the semiconductor gate material in the opening to the channel region portion of the stack of suspended nanowires comprises deposition of a semiconductor material having a composition selected from the group consisting of monocrystalline silicon, polysilicon and combinations thereof, or deposition of an oxide.
18. The method of claim 11 , wherein the applying the surface treatment process to said at least said sidewall surfaces of the second gate structure to convert the portion of the semiconductor gate material to the dielectric spacer on said at least the sidewall surfaces of the second gate structure comprises nitridation, ion implantation, plasma treatments, annealing, and a combination thereof.
19. The method of claim 18 , wherein the reacting the surface treatment process converts said sidewall portion and said upper portion of the second gate structure to a dielectric material, wherein the upper portion of the second gate structure that is converted to the dielectric material is removed by planarization.
20. The method of claim 12 , wherein the replacing of the second replacement gate structure with the functional gate structure comprises:
removing the dielectric coating from exposed portions of the suspended stack that are not covered with the second replacement gate structure;
forming an epitaxial source and drain region semiconductor material on the exposed portions of the suspended stack that are not covered with the second replacement gate structure;
diffusing dopant from the source and drain epitaxial semiconductor material to form source and drain extension regions in the exposed portions of the stack of suspended nanowires;
removing the second replacement gate structure with an etch process; and
forming the functional gate structure in the opening to the channel region portion of the stack of suspended nanowires.