Methods and apparatus to provide an efficient safety mechanism for signal processing hardware

1. A hardware accelerator comprising:

an unprotected memory configured to store a first set of data from an input signal without memory failure protection, wherein failure of any of the first set of data corresponds to corruption of an output data set that is less than or equal to a threshold amount of corruption, and wherein the first set of data includes data from a group consisting of: pixel data, a motion vector, and a stereo disparity;

a protected memory configured to store a second set of data from the input signal with memory failure protection, wherein failure of any of the second set of data corresponds to corruption of the output data set that is more than the threshold amount of corruption, and wherein the second set of data includes data from a group consisting of: a lookup table, protocol information, a filter coefficient, and a statistical value;

logic configured to process the input signal; and

an output interface to output the processed input signal.

2. The hardware accelerator of claim 1 , further including a combinatory logic circuit to process the input signal.

3. The hardware accelerator of claim 1 , wherein the memory failure protection includes at least one of parity protection or error correcting code protection.

4. The hardware accelerator of claim 1 , wherein the threshold amount of corruption is determined based on a level of viewability of the output data set when the output data is displayed.

5. The hardware accelerator of claim 1 , further including a host device to transmit the input signal, the output interface is to transmit the processed input signal to the host device.

6. The hardware accelerator of claim 5 , further including an interface protector to determine redundant bits corresponding to control data of the processed input signal, the output interface to transmit the redundant bits to the host device, the redundant bits generated by the host device.

7. The hardware accelerator of claim 6 , wherein the redundant bits are first redundant bits, the input signal includes second redundant bits in a control signal, and the host device is to:

obtain the second redundant bits from the interface protector;

compare the first redundant bits to the second redundant bits; and

when the first redundant bits do not correspond to the second redundant bits:

determine where an error occurred; and

generate a failure alert corresponding to a faulty hardware element based on where the error occurred.

8. The hardware accelerator of claim 2 , wherein the hardware accelerator is a first hardware accelerator, further including a second hardware accelerator to obtain an output of the first hardware accelerator, the second hardware accelerator including an outlier filter to filter the first set of data to remove error.

9. The hardware accelerator of claim 8 , wherein the error corresponds to at least one of (A) a hardware fault or (B) a bit error in one or more transistors or a logic circuit.

10. The hardware accelerator of claim 8 , wherein the second hardware accelerator combines an outlier filter operation with a pre-existing filter operation.

11. The hardware accelerator of claim 8 , wherein the combinatory logic circuit is to process the input signal prior to filtering the first set of data.

12. The hardware accelerator of claim 8 , wherein the second hardware accelerator replaces a third hardware accelerator dedicated to filtering.

13. The hardware accelerator of claim 8 , wherein the first set of data includes the pixel data, the outlier filter to filter a pixel corresponding to the pixel data by:

determining a neighbor array of pixels neighboring the pixel;

determining an average difference between values of the neighboring pixels and a value of the pixel; and

when the average difference is above a threshold, replacing the value of the pixel with an average value of the neighbor array.

14. A method comprising:

receiving an input signal that includes:

a first set of data that includes at least one of: pixel data, a motion vector, or a stereo disparity; and

a second set of data that includes at least one of: a lookup table, protocol information, a filter coefficient, or a statistical value;

storing the first set of data of the input signal into non-protected memory, the non-protected memory lacking memory failure protection, wherein failure of any of the first set of data corresponds to corruption of an output data set that is less than or equal to a threshold amount of corruption;

storing the second set of data of the input signal into memory including memory failure protection, wherein failure of any of the second set of data corresponds to corruption of the output data set that is more than the threshold amount of corruption;

processing the input signal stored in the protected and non-protected storage; and

transmitting, as the output data set, the processed input signal.

15. The method of claim 14 , wherein the memory failure protection includes at least one of parity protection or error correcting code protection.

16. The method of claim 14 , wherein the threshold amount of corruption is determined based on a level of viewability of the output data set when the output data is displayed.

17. The method of claim 14 , further including transmitting the processed input signal to a host device, the input signal being transmitted by the host device.

18. The method of claim 17 , further including determining redundant bits corresponding to control data of the processed input signal and transmitting the redundant bits to the host device.

19. The method of claim 18 , wherein the redundant bits are first redundant bits, the input signal includes second redundant bits in a control signal, and the method further includes:

obtaining the second redundant bits;

comparing the first redundant bits to the second redundant bits; and

when the first redundant bits do not correspond to the second redundant bits:

determining where an error occurred; and

generating a failure alert corresponding to a faulty hardware element based on where the error occurred.

20. The method of claim 14 , further including filtering the first set of data of the processed signal to remove an error.

21. The method of claim 20 , wherein the error corresponds to at least one of (A) a hardware fault or (B) a bit error in one or more transistors or a logic circuit.

22. The method of claim 20 , wherein the filtering includes an outlier filter operation with a pre-existing filter operation.

23. The method of claim 20 , further including processing the processed signal prior to filtering the first set of data.

24. The method of claim 20 , wherein the first set of data includes the pixel data, and further including filtering a pixel corresponding to the pixel data by:

determining a neighbor array of pixels neighboring the pixel;

determining an average difference between values of the neighboring pixels and a value of the pixel; and

when the average difference is above a threshold, replacing the value of the pixel with an average value of the neighbor array.

25. A non-transitory computer readable medium comprising instructions which, when executed, cause a machine to at least:

receive an input signal that includes:

a first set of data that includes at least one of: pixel data, a motion vector, or a stereo disparity; and

a second set of data that includes at least one of: a lookup table, protocol information, a filter coefficient, or a statistical value;

store the first set of data corresponding to the input signal into memory not including memory failure protection, wherein failure of any of the first set of data corresponds to corruption of an output data set that is less than or equal to a threshold amount of corruption;

store the second set of data corresponding to the input signal into memory failure protected memory, wherein failure of any of the second set of data corresponds to corruption of the output data set that is more than the threshold amount of corruption;

process the input signal stored in the protected and non-protected storage; and

transmit, as the output data set, the processed input signal.

26. The computer readable medium of claim 25 , wherein the threshold amount of corruption is determined based on a level of viewability of the output data set when the output data is displayed.

27. The computer readable medium of claim 25 , wherein the instructions cause the machine to transmit the processed input signal to a host device, the input signal transmitted by the host device.

28. The computer readable medium of claim 27 , wherein the instructions cause the machine to determine redundant bits corresponding to control data of the processed input signal and transmit the redundant bits to the host device.

29. The computer readable medium of claim 28 , wherein the redundant bits are first redundant bits, the input signal includes second redundant bits in a control signal, and the instructions cause the machine to:

obtain the second redundant bits;

compare the first redundant bits to the second redundant bits; and

when the first redundant bits do not correspond to the second redundant bits:

determine where an error occurred; and

generate a failure alert corresponding to a faulty hardware element based on where the error occurred.