System and methods for hardware-software cooperative pipeline error detection
A family of software-hardware cooperative mechanisms to accelerate intra-thread duplication leverage the register file error detection hardware to implicitly check the data from duplicate instructions, avoiding the overheads of instruction checking and enforcing low-latency error detection with strict error containment guarantees.
1. A method comprising:
executing an original instruction;
executing a duplicate instruction of the original instruction;
generating a data portion DI resulting from execution of the original instruction; generating an error correcting code portion ECC I for the data portion DI of the original instruction;
generating an error correcting code portion ECC 2 for a data portion D 2 of the duplicate instruction; and
executing logic to write-back to a register file, and to associate with one another, the data portion DI resulting from execution of the original instruction, and the error correcting code portion ECC 2 for the data portion D 2 resulting from execution of the duplicate instruction.
2. The method of claim 1 , further comprising:
executing error detection on a codeword D 1 /ECC 2 each time DI is read from the register file.
3. The method of claim 1 , further comprising:
executing an instruction set architecture instruction to apply a mask to select either a data portion or an error correcting code portion of a codeword for write-back to the register file.
4. The method of claim 1 , further comprising:
executing logic to write-back to the register file and to associate with one another the data portion D 2 resulting from execution of the duplicate instruction and the error correcting code portion ECC I for the data portion DI resulting from the execution of the original instruction.
5. The method of claim 4 , further comprising:
executing an instruction set architecture instruction to selectively write-back to the register file either a data portion of a codeword or an error correcting code portion of the codeword.
6. The method of claim 4 , further comprising:
providing in the register file a first register set for data portions of codewords; and providing in the register file a second register set separately addressable from the first register set for error correcting code portions of the codewords.
7. The method of claim 4 , further comprising generating error codes at least as indicated in the following table:
D1/E1
D2/E2
D2/E1
Error Type
Likely Cause
0
0
1
DUE
Compute Error
0
1
0
DCE (D1/E1)
Storage Error in E2
1
0
0
DCE (D1/E2)
Storage Error in D1.
8. The method of claim 4 , further comprising generating error codes at least as indicated in the following table:
D1/E1
D2/E2
D2/E1
Error Type
Likely Cause
0
0
0
DUE
Unknown/Invalid
0
0
1
DUE
Compute Error
0
1
0
DCE (D1/E1)
Storage Error in E2
0
1
1
DCE (D1/E1)
Double Event in D2/E2
1
0
0
DCE (D1/E2)
Storage Error in D1
1
0
1
DCE (D2/E2)
Double Event in D1/E1
1
1
0
DUE
Multibit Error in D1/E2
1
1
1
DUE
Multibit Error in D1/D2
or E1/E2.
9. The method of claim 1 , further comprising:
predicting one or both of ECC I or ECC 2 for 64 bit operands for the original instruction or duplicate instruction by merging a plurality of 32 bit residue codes for the operands into a 64 bit residue code prior to prediction of ECC 1 or ECC 2 .
10. The method of claim 9 , further comprising:
re-encoding any greater than 32 residue codes into a plurality of codewords each 32 bits long for write-back to the register file.
11. A processor, comprising:
logic to execute an original instruction and to execute a duplicate instruction of the original instruction;
logic to generate a data portion DI resulting from execution of the original instruction;
logic to generate an error correcting code portion ECC I for the data portion DI of the original instruction;
logic to generate an error correcting code portion ECC 2 for a data portion D 2 of the duplicate instruction; and
logic to write-back to a register file and to associate with one another the data portion DI resulting from execution of the original instruction and the error correcting code portion ECC 2 for the data portion D 2 resulting from execution of the duplicate instruction.
12. The processor of claim 11 , wherein the processor further comprises:
logic to execute error detection on a codeword D 1 /ECC 2 each time DI is read from the register file.
13. The processor of claim 11 , wherein the processor further comprises:
logic to execute an instruction to apply a mask to select either a data portion of a codeword or an error correcting code portion of the codeword for write-back to the register file.
14. The processor of claim 11 , wherein the processor further comprises:
logic to write-back to the register file and to associate with one another the data portion D 2 resulting from execution of the duplicate instruction and the error correcting code portion ECC I for the data portion DI resulting from execution of the original instruction.
15. The processor of claim 14 , wherein the processor further comprises:
logic to execute an instruction to selectively write-back to the register file either a data portion of a codeword or an error correcting code portion of the codeword.
16. The processor of claim 14 , wherein the processor further comprises:
a first register set for data portions of codewords; and
a second register set separately addressable from the first register set for error correcting code portions of the codewords.
17. The processor of claim 14 , wherein the processor further comprises logic to generate error codes at least as indicated in the following table:
D1/E1
D2/E2
D2/E1
Error Type
Likely Cause
0
0
1
DUE
Compute Error
0
1
0
DCE (D1/E1)
Storage Error in E2
1
0
0
DCE (D1/E2)
Storage Error in D1.
18. The processor of claim 14 , wherein the processor further comprises logic to generate error codes as indicated in the following table:
D1/E1
D2/E2
D2/E1
Error Type
Likely Cause
0
0
0
DUE
Unknown/Invalid
0
0
1
DUE
Compute Error
0
1
0
DCE (D1/E1)
Storage Error in E2
0
1
1
DCE (D1/E1)
Double Event in D2/E2
1
0
0
DCE (D1/E2)
Storage Error in D1
1
0
1
DCE (D2/E2)
Double Event in D1/E1
1
1
0
DUE
Multibit Error in D1/E2
1
1
1
DUE
Multibit Error in D1/D2
or E1/E2.
19. The processor of claim 11 , wherein the processor further comprises:
logic to predict one or both of ECC I or ECC 2 for 64 bit operands for the original instruction or duplicate instruction by merging a plurality of 32 bit residue codes for the operands into a 64 bit residue code prior to prediction of ECC 1 or ECC 2 .
20. The processor of claim 19 , wherein the processor further comprises:
logic to re-encode any greater than 32 residue codes into a plurality of codewords each 32 bits long for write-back to the register file.