Trench silicide contacts with high selectivity process
A method for forming self-aligned contacts includes patterning a mask between fin regions of a semiconductor device, etching a cut region through a first dielectric layer between the fin regions down to a substrate and filling the cut region with a first material, which is selectively etchable relative to the first dielectric layer. The first dielectric layer is isotropically etched to reveal source and drain regions in the fin regions to form trenches in the first material where the source and drain regions are accessible. The isotropic etching is super selective to remove the first dielectric layer relative to the first material and relative to gate structures disposed between the source and drain regions. Metal is deposited in the trenches to form silicide contacts to the source and drain regions.
1. A method for forming self-aligned contacts, comprising:
forming a cut region in a first dielectric layer between semiconductor fin regions of a semiconductor substrate by removing a portion of the first dielectric layer;
filling the cut region with a second dielectric material, which is selectively etchable relative to the first dielectric layer;
forming a co-planar surface across the second dielectric material and the first dielectric layer by planarizing the second dielectric material down to a top surface of the first dielectric layer;
forming and patterning a third dielectric layer on the co-planar surface to expose portions of the first dielectric layer;
isotropicly etching the exposed portions of the first dielectric layer to form trenches that expose source and drain regions in the fin regions, the isotropic etching being super selective with an etch ratio of 100:1 or greater to remove the first dielectric layer relative to the second dielectric material, the third dielectric layer and gate structures, the gate structures being disposed between the source and drain regions; and
depositing metal in the trenches to form contacts to the source and drain regions.
2. The method as recited in claim 1 , wherein the isotropic etching includes one of a buffered hydrofluoric (BHF) etch or a chemical oxide removal (COR) process.
3. The method as recited in claim 1 , wherein the first dielectric layer includes a silicon oxide and the second dielectric material includes a silicon nitride.
4. The method as recited in claim 1 , wherein the contacts have a first width at a first level in contact with the source and drain regions that is larger than a second width at a second level at a top surface of the second dielectric material.
5. The method as recited in claim 1 , wherein the contacts include angled lateral sides below a surface of the second dielectric material such that the contacts are narrower near the surface of the second dielectric material than near the source and drain regions.
6. The method as recited in claim 1 , wherein the third dielectric layer includes amorphous carbon.
7. The method as recited in claim 1 , wherein the contacts include a first portion up to a height of the gate structures and an extended portion that extends above the gate structures.
8. The method as recited in claim 7 , wherein the extended portions are separated by the third dielectric layer.