Semiconductor device
View Patent ↗A semiconductor device includes: a substrate having a first semiconductor layer, an insulating layer, and a second semiconductor layer; an active device on the substrate; an interlayer dielectric (ILD) layer on the active device; a first contact plug adjacent to the active device; and a second contact plug in the ILD layer and electrically connected to the active device. Preferably, the first contact plug includes a first portion in the insulating layer and the second semiconductor layer and a second portion in the ILD layer, in which a width of the second portion is greater than a width of the first portion.
1. A semiconductor device, comprising:
a substrate, wherein the substrate comprises a first semiconductor layer, an insulating layer, and a second semiconductor layer;
an active device on the substrate;
a shallow trench isolation (STI) around the active device;
an interlayer dielectric (ILD) layer on the active device;
a first contact plug adjacent to the active device, wherein the first contact plug comprises:
a first portion in the insulating layer and the STI and contacting the STI directly; and
a second portion in the ILD layer, wherein a width of the second portion is greater than a width of the first portion;
a second contact plug in the ILD layer and electrically connected to the active device; and
a contact etch stop layer (CESL) on the active device and the substrate, wherein the CESL contacts the first portion and the second portion directly.
2. The semiconductor device of claim 1 , wherein the active device comprises:
a gate structure on the second semiconductor layer; and
a source/drain region adjacent to two sides of the gate structure and in the second semiconductor layer.
3. The semiconductor device of claim 1 , wherein a width of the first portion is greater than a width of the second contact plug.
4. The semiconductor device of claim 1 , wherein a width of the second portion is greater than a width of the second contact plug.
5. The semiconductor device of claim 1 , wherein the top surfaces of the second portion and the second contact plug are coplanar.
6. A semiconductor device, comprising:
a substrate, wherein the substrate comprises a first semiconductor layer, an insulating layer, and a second semiconductor layer;
an active device on the substrate;
an interlayer dielectric (ILD) layer on the active device;
a first contact plug adjacent to the active device, wherein the first contact plug comprises:
a first portion in the insulating layer and the second semiconductor layer; and
a second portion in the ILD layer, wherein a width of the second portion is greater than a width of the first portion;
a second contact plug in the ILD layer and electrically connected to the active device; and
a contact etch stop layer (CESL) on the active device and the substrate, wherein the CESL not contacting the second portion directly and a bottom surface of the CESL not contacting the second portion directly is even with a bottom surface of the second portion.
7. The semiconductor device of claim 6 , wherein the active device comprises:
a gate structure on the second semiconductor layer; and
a source/drain region adjacent to two sides of the gate structure and in the second semiconductor layer.
8. The semiconductor device of claim 7 , further comprising a shallow trench isolation (STI) around the source/drain region.
9. The semiconductor device of claim 6 , wherein a width of the first portion is greater than a width of the second contact plug.
10. The semiconductor device of claim 6 , wherein a width of the second portion is greater than a width of the second contact plug.
11. The semiconductor device of claim 6 , wherein the top surfaces of the second portion and the second contact plug are coplanar.