Resistive memory with a plurality of resistive random access memory cells each comprising a transistor and a resistive element

1. A method of forming a semiconductor structure, comprising:

forming a plurality of vertical field-effect transistors (VFETs) disposed on a substrate; and

forming a plurality of resistive elements disposed over top surfaces of the VFETs;

wherein each pair of a given one of the plurality of VFETs and a corresponding resistive element disposed over the given VFET provides a resistive random access memory (ReRAM) cell;

wherein the VFETs are arranged in two or more columns and two or more rows;

wherein each column of VFETs provides a bitline of the ReRAM cells sharing a bottom source/drain region;

wherein each row of VFETs provides a wordline of the ReRAM cells sharing a gate; and

wherein top source/drain regions of the VFETs provide bottom contacts for the resistive elements disposed over the VFETs;

wherein forming the plurality of VFETs comprises:

forming a doped layer disposed over a top surface of the substrate;

forming a channel layer disposed over a top surface of the doped layer;

forming a hard mask layer disposed over a top surface of the channel layer;

patterning the hard mask layer to expose portions of the channel layer;

etching exposed portions of the channel layer, the doped layer and portions of the substrate to form two or more fins;

forming shallow trench isolation regions disposed over the top surface of the substrate surrounding the two or more fins;

forming a mask layer disposed over the two or more fins;

patterning the mask layer to expose portions of the hard mask layer of the two or more fins;

etching exposed portions of the hard mask layer and the channels of the two or more fins to form a plurality of pillars disposed over the doped layers of the two or more fins, wherein the doped layer of each of the two or more fins provides the bottom source/drain region for a given one of the bitlines;

forming bottom spacers disposed over the shallow trench isolation regions;

forming a gate dielectric disposed over the shallow trench isolation regions and surrounding portions of the channel layer of the plurality of pillars; and

forming a gate conductor disposed over the gate dielectric.

2. The method of claim 1 , wherein forming the plurality of VFETs further comprises:

forming a gate mask layer over the gate conductor and the gate dielectric;

patterning the gate mask layer; and

etching the gate dielectric and the gate conductor exposed by the gate mask layer to form gates for the rows of VFETs.

3. The method of claim 2 , wherein forming the plurality of VFETs further comprises:

forming top spacers disposed over the gate conductor, the gate dielectric and surrounding the channel layer and the hard mask layer of the plurality of pillars; and

forming an interlevel dielectric layer disposed over the top spacers.

4. The method of claim 3 , wherein forming the plurality of VFETs further comprises:

removing the hard mask layer disposed over each of the pillars;

recessing the channel layer to a bottom surface of the top spacers; and

forming top/source drain regions over top surfaces of the recessed channel layers.

5. The method of claim 4 , wherein forming the plurality of VFETs further comprises performing dopant drive in to form junctions of the top source/drain regions and the recessed channel layers.

6. The method of claim 4 , wherein forming the plurality of resistive elements comprises:

forming bottom electrodes disposed over top surfaces of the top source/drain regions;

forming switch material disposed over top surfaces of the bottom electrodes and on portions of the sidewalls of the top spacers of each of the plurality of pillars; and

forming top electrodes disposed over the switch material.

7. The method of claim 6 , wherein the bottom electrodes comprise nitrogen-rich titanium nitride (TiN), the switch material comprises hafnium oxide (HfOx), and the top electrodes comprise titanium-rich TiN.

8. The method of claim 6 , wherein forming the plurality of resistive elements further comprises forming top contacts disposed over top surfaces of the top electrodes.

9. A semiconductor structure, comprising:

a plurality of vertical field-effect transistors (VFETs) disposed on a substrate; and

a plurality of resistive elements disposed over top surfaces of the VFETs;

wherein each pair of a given one of the plurality of VFETs and a corresponding resistive element disposed over the given VFET provides a resistive random access memory (ReRAM) cell;

wherein the VFETs are arranged in two or more columns and two or more rows;

wherein each column of VFETs provides a bitline of the ReRAM cells sharing a bottom source/drain region;

wherein each row of VFETs provides a wordline of the ReRAM cells sharing a gate;

wherein top source/drain regions of the VFETs provide bottom contacts for the resistive elements disposed over the VFETs; and

wherein the VFETs comprise:

a plurality of fins disposed over the substrate, each of the plurality of fins comprising a doped layer disposed over the substrate providing the bottom source/drain regions for a respective bitline of the ReRAM cells;

shallow trench isolation regions disposed over the substrate surrounding the doped layer of each of the plurality of fins;

a plurality of pillars disposed over each of the fins, each pillar comprising a channel disposed over the doped layer and one of the top source/drain region disposed over the channel;

bottom spacers disposed over the shallow trench isolation regions surrounding the fins and disposed over the doped layer surrounding the pillars;

the gates formed over the bottoms spacers surrounding each of the pillars, each of the gates comprising a gate dielectric and a gate conductor disposed surrounding a row of the pillars providing a respective wordline of the ReRAM cells;

top spacers disposed over the plurality of gates surrounding each of the pillars;

an interlevel dielectric disposed over the top spacers surrounding each of the pillars; and

the top source/drain regions disposed over the channel in each of the pillars.

10. The semiconductor structure of claim 9 , wherein the resistive elements comprise:

bottom electrodes disposed over the top source/drain regions of the VFETs;

a switch material disposed over the bottom electrodes and a portion of sidewalls of the top spacers;

top electrodes disposed over the switch material; and

top contacts formed over the top electrodes.

11. The semiconductor structure of claim 10 , wherein the bottom electrodes comprise nitrogen-rich titanium nitride (TiN), the switch material comprises hafnium oxide (HfOx), and the top electrodes comprise titanium-rich TiN.

12. An integrated circuit comprising:

a resistive random access memory (ReRAM) device comprising a plurality of ReRAM cells, each of the plurality of ReRAM cells comprising:

a given one of a plurality of vertical field-effect transistors (VFETs) disposed on a substrate; and

a given one of a plurality of resistive elements disposed over a top surface of the given VFET;

wherein the VFETs are arranged in two or more columns and two or more rows;

wherein each column of VFETs provides a bitline of the ReRAM cells sharing a bottom source/drain region;

wherein each row of VFETs provides a wordline of the ReRAM cells sharing a gate;

wherein top source/drain regions of the VFETs provide bottom contacts for the resistive elements disposed over the VFETs; and

wherein the VFETs comprise:

a plurality of fins disposed over the substrate, each of the plurality of fins comprising a doped layer disposed over the substrate providing the bottom source/drain regions for a respective bitline of the ReRAM cells;

shallow trench isolation regions disposed over the substrate surrounding the doped layer of each of the plurality of fins;

a plurality of pillars disposed over each of the fins, each pillar comprising a channel disposed over the doped layer and one of the top source/drain region disposed over the channel;

bottom spacers disposed over the shallow trench isolation regions surrounding the fins and disposed over the doped layer surrounding the pillars;

a plurality of gates formed over the bottoms spacers surrounding each of the pillars, each of the plurality of gates comprising a gate dielectric and a gate conductor disposed surrounding a row of the pillars providing a respective wordline of the ReRAM cells;

top spacers disposed over the plurality of gates surrounding each of the pillars;

an interlevel dielectric disposed over the top spacers surrounding each of the pillars; and

the top source/drain regions disposed over the channel in each of the pillars.

13. The integrated circuit of claim 12 , wherein the resistive elements comprise:

bottom electrodes disposed over the top source/drain regions;

a switch material disposed over the bottom electrodes and a portion of sidewalls of the top spacers;

top electrodes disposed over the switch material; and

top contact formed over the top electrodes.

14. The integrated circuit of claim 13 , wherein the bottom electrodes comprise nitrogen-rich titanium nitride (TiN), the switch material comprises hafnium oxide (HfOx), and the top electrodes comprise titanium-rich TiN.