Physical unclonable function (PUF) chip and fabrication method thereof
A physical unclonable function (PUF) chip and a fabrication method are provided. The fabrication method includes: forming an array of spaced electrode plates on a top metal connection layer of a nude chip, while forming the top metal connection layer; forming a deposition layer, on the top metal connection layer between adjacent electrode plates; forming openings between adjacent electrode plates in a row, each opening having a circumference tangent to the adjacent electrode plates; coating a conductive coating layer on the nude chip, the conductive coating layer including conductive particles with randomly distributed size; and packaging the nude chip to provide the PUF chip.
1. A method of fabricating a physical unclonable function (PUF) chip, comprising:
forming a top metal connection layer of a chip;
forming an array of spaced electrode plates on the top metal connection layer of the chip;
forming a deposition layer, on the top metal connection layer between each two adjacent electrode plates;
forming an opening in the deposition layer between each two adjacent electrode plates in a row, wherein each two adjacent electrode plates are tangential to the opening formed between the two adjacent electrode plates;
coating a conductive coating layer on the chip, the conductive coating layer including conductive particles with randomly distributed size to form randomly distributed bridges between adjacent two electrode plates; and
packaging the chip to provide the PUF chip.
2. The method according to claim 1 , wherein forming the array of spaced electrode plates on the top metal connection layer comprises:
providing a comb-shaped mask pattern when forming the top metal connection layer of the chip; and
exposing the nude chip to form the array of spaced electrode plates.
3. The method according to claim 1 , wherein:
the conductive coating layer is coated in a region of the openings.
4. The method according to claim 1 , wherein:
the deposition layer is formed between adjacent electrode plates in any row by an in-mold decoration (IMD) process.
5. The method according to claim 1 , further comprising:
detecting a connection state of a capacitor, formed by the adjacent electrode plates in a row having the deposition layer there-between; and
storing a detection result in a storage unit of the PUF chip.
6. The method according to claim 5 , wherein:
the storage unit is a nonvolatile memory.
7. The method according to claim 1 , wherein:
the electrode plates in the array of spaced electrode plates have a same size.
8. The method according to claim 1 , wherein:
the adjacent electrode plates in any row of the array of spaced electrode plates are arranged at equal intervals.
9. The method according to claim 1 , wherein:
a capacitor formed by the bridged adjacent two electrode plates is in a bridged capacitor state, and
a capacitor formed by non-bridged adjacent two electrode plates is in a normal capacitor state.
10. The method according to claim 1 , wherein:
the conductive coating layer is directly formed in each of the openings in the deposition layer.
11. The method according to claim 1 , wherein:
the bridged adjacent two electrode plates are electrically connected by conductive particles distributed between the bridged adjacent two electrode plates.