Supporting adaptive shared cache management
Embodiment of this disclosure provides a mechanism to use a portion of an inactive processing element's private cache as an extended last-level cache storage space to adaptively adjust the size of shared cache. In one embodiment, a processing device is provided. The processing device comprising a cache controller is to identify a cache line to evict from a shared cache. An inactive processing core is selected by the cache controller from a plurality of processing cores associated with the shared cache. Then, a private cache of the inactive processing core is notified of an identifier of a cache line associated with the shared cache. Thereupon, the cache line is evicted from the shared cache to install in the private cache.
1. A processing device comprising:
a plurality of processing cores; and
a cache controller, operatively coupled to the processing cores, to:
determine a cache line to evict from a shared cache;
select an inactive processing core of the plurality of processing cores associated with the shared cache;
transmit, to a private cache of the inactive processing core, a message to initiate a prefetch of the cache line by the private cache of the inactive processing core; and
forward the cache line from the shared cache to the private cache.
2. The processing device of claim 1 , wherein the cache controller is further to identify the cache line based on a counter associated with the shared cache.
3. The processing device of claim 2 , wherein the counter indicates that the identified cache line is a least-recently-used (LRU) memory space of the shared cache.
4. The processing device of claim 1 , wherein the cache controller is further to:
receive an access request with respect to the cache line; and
forward the memory request to the private cache of the inactive processing core to retrieve the cache line.
5. The processing device of claim 1 , wherein the request comprises the identifier of the cache line.
6. The processing device of claim 1 , wherein the cache controller is further to trigger an eviction of the cache line in the private cache of the inactive processing core to main memory.
7. The processing device of claim 1 , further comprising a memory device to implement the shared cache, wherein the shared cache is shared by the plurality of processing cores.
8. A method comprising:
determining, by a processing device, a cache line to evict from a shared cache;
selecting, by the processing device, an inactive processing core of a plurality of processing cores associated with the shared cache;
transmitting, by the processing device, a private cache of the inactive processing core, a message to initiate a prefetch of the cache line by the private cache of the inactive processing core; and
forwarding, by the processing device, the cache line from the shared cache to the private cache.
9. The method of claim 8 , further comprising identifying the cache line based on a counter associated with the shared cache.
10. The method of claim 9 , wherein the counter indicates that the identified cache line is a least-recently-used (LRU) memory space of the shared cache.
11. The method of claim 8 , further comprising:
receiving an access request with respect to the cache line; and
forwarding the memory request to the private cache of the inactive processing core to retrieve the cache line.
12. The method of claim 8 , wherein the request comprises the identifier of the cache line.
13. The method of claim 8 , further comprising triggering an eviction of the cache line in the private cache of the inactive processing core to main memory.
14. A system comprising:
a shared cache to store a plurality of cache lines; and
a processing device, operatively coupled to the shared cache, to:
determine a cache line to evict from a shared cache;
select an inactive processing core of a plurality of processing cores associated with the shared cache;
transmit, to a private cache of the inactive processing core, a message to initiate a prefetch of the cache line by the private cache of the inactive processing core; and
forward the cache line from the shared cache to the private cache.
15. The system of claim 14 , wherein the processing device is further to identify the cache line based on a counter associated with the shared cache.
16. The system of claim 15 , wherein the counter indicates that the identified cache line is a least-recently-used (LRU) memory space of the shared cache.
17. The system of claim 14 , wherein the processing device is further to:
receive an access request with respect to the cache line; and
forward the memory request to the private cache of the inactive processing core to retrieve the cache line.