IP Library › Granted Patent US 10,283,175
Granted Patent B1
US 10,283,175 · App. 15/853,841 · Granted May 7, 2019

NAND flash memory and status output method in NAND flash memory

Inventor: Minyi Chen (San Jose, CA)
Assignees: GIGADEVICE SEMICONDUCTOR (SHANGHAI) INC.; GIGADEVICE SEMICONDUCTOR (BEIJING) INC.; GIGADEVICE SEMICONDUCTOR (HEFEI) INC.
G11C7/1063G11C7/1057G11C7/1096G11C7/222G11C16/32
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Quick Facts
Patent No.
US 10,283,175
App. No.
15/853,841
Granted
May 7, 2019
Kind
B1
Abstract

The present application provides a status output method in NAND flash memory, including, setting ALE signal, CLE signal and WE#, signal wherein ALE and/or CLE signal is set to be 1 and WE# signal is set to be 1; when a falling edge of the RE# is detected, outputting LUN status signal of the NAND flash memory. Further, there is provided a NAND flash memory, including I/O signal pins, which includes an ALE signal pin, an CLE signal pin, a WE# signal pin, and a RE# signal pin; wherein when the ALE signal output by the ALE pin and/or CLE signal output by the CLE pin is 1, and WE# signal output by the WE# pin is 1, once a falling edge of the RE# is detected, the LUN status signal of the NAND flash memory is detected.

Claims (12)

1. A status output method in NAND flash memory, comprising:

setting an address latch enable (ALE) signal, a command latch enable (CLE) signal and a write enable (WE#) signal, wherein the address latch enable (ALE) signal and/or the command latch enable (CLE) signal is set to be 1 and the write enable (WE#) signal is set to be 1;

when a falling edge of a read enable (RE#) is detected, outputting a logic unit (LUN) status signal of the NAND flash memory;

wherein,

when the address latch enable (ALE) signal and/or the command latch enable (CLE) signal is detected to be 1, storing the logic unit (LUN) status signal in a storage area of the NAND flash memory.

2. The status output method according to claim 1 , wherein the storage area is a register.

3. A NAND flash memory, comprising:

I/O signal pins, including an address latch enable (ALE) pin, a command latch enable (CLE) pin, a write enable (WE#) pin, and a read enable (RE#) pin;

wherein when an ALE signal outputted by the address latch enable (ALE) pin and/or a CLE signal outputted by the command latch enable (CLE) pin is 1, and a WE# signal outputted by the write enable (WE#) pin is 1, once a falling edge of the read enable (RE#) pin is detected, a logic unit (LUN) status signal of the NAND flash memory is detected;

wherein the NAND flash memory further comprises a storage for storing the logic unit (LUN) status signal of the NAND flash memory.

4. The NAND flash memory according to claim 3 , wherein the storage is a register.

5. The NAND flash memory according to claim 3 , wherein the NAND flash memory is a multi-die package NAND flash memory.

Assignments (3)
CHANGE OF NAME & ADDRESS Recorded Oct 13, 2022
From: GIGADEVICE SEMICONDUCTOR (BEIJING) INC.
To: GIGADEVICE SEMICONDUCTOR INC.
Reel/Frame 061668/0819 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 13, 2019
From: SHINE BRIGHT TECHNOLOGY LIMITED
To: GIGADEVICE SEMICONDUCTOR (SHANGHAI) INC.; GIGADEVICE SEMICONDUCTOR (BEIJING) INC.; GIGADEVICE SEMICONDUCTOR (HEFEI) INC.
Reel/Frame 048580/0054 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 24, 2017
From: CHEN, MINYI
To: SHINE BRIGHT TECHNOLOGY LIMITED
Reel/Frame 044957/0228 →