IP Library Granted Patent US 10,312,914
Granted Patent B2
US 10,312,914 · App. 15/854,515 · Granted Jun 4, 2019

Gate driver with serial communication

Inventors: Xiong Li (Allen, TX); Toru Tanaka (Plano, TX)
Assignee: TEXAS INSTRUMENTS INCORPORATED
H03K19/0952H02M7/537H03K5/19H03K17/063H03K17/223H03K19/01707
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,312,914
App. No.
15/854,515
Granted
Jun 4, 2019
Kind
B2
Abstract

A gate driver includes a drive signal input terminal, a drive signal output terminal, a gate drive circuit, and a serial communication interface. The drive signal input terminal is configured to receive a gate drive signal. The gate drive circuit is coupled to the drive signal input terminal and the drive signal output terminal. The gate drive circuit is configured to provide the gate drive signal to the drive signal output terminal. The serial communication interface is coupled to the drive signal input terminal.

Claims (48)

1. A gate driver, comprising:

a drive signal input terminal configured to receive a gate drive signal;

a drive signal output terminal;

a gate drive circuit coupled to the drive signal input terminal and the drive signal output terminal, the gate drive circuit configured to provide the gate drive signal to the drive signal output port; and

a serial communication interface coupled to the drive signal input terminal,

wherein:

the gate drive circuit is configured to amplify the gate drive signal; and

the serial communication interface comprises:

a data input terminal; and

control circuitry configured to assign a value received via the data input terminal to be an address of the serial communication interface responsive to activation of the gate drive signal.

2. The gate driver of claim 1 , wherein the control circuitry is configured to enter an address initialization mode and remain in the address initialization mode until the gate drive signal is activated and thereafter deactivated.

3. The gate driver of claim 2 , wherein the control circuitry is configured to:

transition from the address initialization mode to an operation mode responsive to assignment of the address; and

enable operation of the serial communication interface responsive to receipt, via the data input terminal, of an address value that matches the address assigned to the serial communication interface.

4. The gate driver of claim 1 , wherein the control circuitry is configured to apply the gate drive signal to enable operation of the serial communication interface during the address initialization mode.

5. The gate driver of claim 4 , wherein the control circuitry is configured to apply the signal at the select terminal in conjunction with the gate drive signal to enable operation of the serial communication interface while the serial communication interface is in the address initialization mode.

6. The gate driver of claim 1 , wherein the serial communication interface comprises a select terminal, and the control circuitry is configured to apply a signal at the select terminal to enable operation of the serial communication interface after the address is assigned to the serial communication interface.

7. A motor drive circuit, comprising:

a plurality of power transistors configured to drive an electric motor; and

a plurality of gate drivers, one of the gate drivers connected to a control terminal of each of the power transistors, each of the gate drivers comprising:

a drive signal input terminal;

a gate drive circuit coupled to the drive signal input terminal, the gate drive circuit configured to drive a signal received at the drive signal input terminal to the control terminal of the one of the power transistors connected to the gate driver;

a serial communication interface coupled to the gate drive circuit, the serial communication interface comprising:

a data input terminal; and

control circuitry configured to:

enter an address initialization mode during initialization of the gate driver; and

remain in the address initialization mode until the signal received at the drive signal input terminal is activated and thereafter deactivated.

8. The motor drive circuit of claim 7 , wherein the control circuitry is configured to assign a value received via the data input terminal to be an address of the serial communication interface responsive to the activation of a signal at the drive signal input terminal.

9. The motor drive circuit of claim 8 , wherein the control circuitry is configured to transition from the address initialization mode to an operation mode responsive to assignment of the address.

10. The motor drive circuit of claim 9 , wherein the control circuitry is configured to enable operation of the serial communication interface responsive to receipt, via the data input terminal, of an address value that matches the address assigned to the serial communication interface.

11. The motor drive circuit of claim 7 , wherein the control circuitry is configured to apply the signal at the drive signal input terminal to enable operation of the serial communication interface during the address initialization mode.

12. The motor drive circuit of claim 7 , wherein the serial communication interface comprises a select terminal, and the control circuitry is configured to apply the signal at the select terminal to enable operation of the serial communication interface after termination of the address initialization mode.

13. The motor drive circuit of claim 7 , wherein the control circuitry is configured to apply the signal at the select terminal in conjunction with the signal at the drive signal input terminal to enable operation of the serial communication interface while the serial communication interface is in the address initialization mode.

14. The motor drive circuit of claim 7 , wherein, while in the address initialization mode, the control circuitry is configured to disregard the signal at the data input terminal until the signal at the drive signal input terminal is activated.

15. A traction inverter, comprising:

a plurality of power transistors configured to drive an electric motor;

a plurality of gate drivers, each of the gate drivers connected to a control terminal of one of the power transistors; and

a controller comprising a plurality of motor drive terminals, each of the motor drive terminals connected to a drive signal input terminal of one of the gate drivers;

wherein each of the gate drivers comprises a serial communication interface coupled to the controller, the serial communication interface comprising:

a data input terminal; and

control circuitry configured to:

enter an address initialization mode during initialization of the gate driver;

remain in the address initialization mode until a signal received at the drive signal input terminal is activated and thereafter inactivated; and

while in the address initialization mode, assign a value received via the data input terminal to be an address of the serial communication interface.

16. The traction inverter of claim 15 , wherein the control circuitry is configured to apply the signal at the drive signal input terminal to enable operation of the serial communication interface during the address initialization mode.

17. The traction inverter of claim 15 , wherein the serial communication interface comprises a select terminal coupled to the controller, and the control circuitry is configured to apply the signal at the select terminal to enable operation of the serial communication interface after termination of the address initialization mode.

18. The traction inverter of claim 17 , wherein the control circuitry is configured to enable operation of the serial communication interface responsive to receipt, via the data input terminal, of an address value that matches the address assigned to the serial communication interface.

19. The traction inverter of claim 15 , wherein the control circuitry is configured to transition from the address initialization mode to an operation mode responsive to assignment of the address.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2018
From: LI, XIONG; TANAKA, TORU
To: TEXAS INSTRUMENTS INCORPORATED
Reel/Frame 044580/0580 →
Continuity (2)
Provisional Application 62510066 · May 23, 2017
Related Publication 20180343009A1 · Nov 29, 2018