Semiconductor device including buried gate structure and method for fabricating the same
A semiconductor device includes: a gate trench formed into a semiconductor substrate; a gate dielectric layer formed in the gate trench to cover an inside surface of the gate trench; and a gate electrode disposed over the gate dielectric layer to fill the gate trench, wherein the gate electrode includes: second crystal grains formed in the gate trench; and first crystal grains disposed between the second crystal grains and the gate dielectric layer and having a smaller crystal grain size than the second crystal grains.
1. A semiconductor device, comprising:
a gate trench formed into a semiconductor substrate;
a first doping region and a second doping region formed in the substrate separated from each other by the gate trench;
a gate dielectric layer formed in the gate trench to cover an inside surface of the gate trench; and
a gate electrode disposed over the gate dielectric layer to fill a lower part of the gate trench without overlapping with the first and the second doping region,
wherein the gate electrode includes:
a second crystal grain layer disposed in the gate trench, the second crystal grain layer having second crystal grains; and
a first crystal grain layer disposed between the second crystal grain layer and the gate dielectric layer, the first crystal grain layer having first crystal grains, and is directly contacted with the second crystal grain layer,
wherein each of the first crystal grains has a smaller crystal grain size than each of the second crystal grains,
wherein the first crystal grains and the second crystal grains are a columnar structure, and
wherein the gate electrode having the columnar structure comprises the first and second crystal grains,
wherein the first crystal grain layer is a polycrystalline layer free of any voids formed by a crystal grain growth of an amorphous material,
wherein the second crystal grain layer is formed by a crystal grain growth of a polycrystalline material, and
wherein said crystal growth includes annealing the amorphous and the polycrystalline materials at a temperature of from 300° C. to 1100° C.
2. The semiconductor device of claim 1 , wherein the first crystal grains and the second crystal grains are crystal grains of the same material.
3. The semiconductor device of claim 1 , wherein the first crystal grains and the second crystal grains include metal crystal grains or metal nitride crystal grains.
4. The semiconductor device of claim 1 , wherein the first crystal grains and the second crystal grains include titanium nitride (TiN) crystal grains, respectively.
5. The semiconductor device of claim 1 , further comprising:
a fin region formed on a bottom surface of the gate trench and including an upper surface and side walls covered by the gate dielectric layer,
wherein the first crystal grains cover the upper surface and side walls of the fin region.
6. The semiconductor device of claim 1 , wherein the first crystal grains cover the gate dielectric layer, and the second crystal grains do not contact the gate dielectric layer.
7. The semiconductor device of claim 1 , further comprising:
a capping layer formed on the gate electrode inside the gate trench to fill an upper part of the gate trench, and wherein the gate electrode filling a lower part of the gate trench.
8. The semiconductor device of claim 1 , wherein the first crystal grains and the second crystal grains are formed of metal nitride.
9. The semiconductor device of claim 1 , wherein the first crystal grains and the second crystal grains are formed of metal.
10. The semiconductor device of claim 1 , wherein the amorphous material is formed of an amorphous titanium nitride, and the polycrystalline material is formed of polycrystalline titanium nitride.
11. The semiconductor device of claim 1 , wherein the gate electrode is formed of only titanium nitride.