NAND flash memory and method for destroying information from the NAND flash memory

1. A NAND flash memory, comprising:

a control unit, wherein the control unit includes a signal receiving circuit, a voltage boosted circuit and a flash array;

a power source supplying power to the control unit;

wherein the signal receiving circuit is configured to transmit an erase signal to the voltage boosted circuit; the voltage boosted circuit configured to exert a device erase pulse of a magnitude larger than an initial voltage to blocks of the flash array to permanently erase data in the blocks and destroy a floating gate; the blocks include power-on read blocks and the erase signal comprises three sub-signals including a voltage boost sub-signal, an erase pulse timing sub-signal and a block selecting sub-signal; the voltage boost sub-signal sets the magnitude of the device erase pulse; the erase pulse timing sub-signal sets a pulse width of the device erase pulse; and the block selecting sub-signal selects the blocks of the flash array to permanently erase data.

2. The NAND flash memory according to claim 1 , wherein the signal receiving circuit is configured to receive a device erase command from an external NAND controller.

3. The NAND flash memory according to claim 1 , wherein the pulse width of the device erase pulse is 0.5 seconds to 10 seconds.

4. The NAND flash memory according to claim 1 , wherein the device erase pulse magnitude is between 20 volts and 30 volts.

5. The NAND flash memory according to claim 1 , wherein the device erase pulse is a single erase pulse.

6. The NAND flash memory according to claim 1 , wherein the control unit receives a device erase command and the control unit decodes the device erase command.

7. A method for destroying information from a NAND flash memory, the method comprising:

receiving an erase signal by a voltage boosted circuit;

the voltage boosted circuit exerting a device erase pulse of a magnitude higher than an initial voltage to blocks of a flash array to permanently erase data in the blocks and destroy a floating gate;

wherein the NAND flash memory comprises a control unit, and a power source supplying power to the control unit;

wherein the control unit includes a signal receiving circuit, the voltage boosted circuit and the flash array;

wherein the signal receiving circuit transmits the erase signal to the voltage boosted circuit;

the blocks include power-on read blocks and the erase signal comprises three sub-signals including a voltage boost sub-signal, an erase pulse timing sub-signal and a block selecting sub-signal; the voltage boost sub-signal sets the magnitude of the device erase pulse; the erase pulse timing sub-signal sets a pulse width of the device erase pulse; and the block selecting sub-signal selects the blocks of the flash array to permanently erase data.

8. The method according to claim 7 , wherein the method further comprises an external NAND controller sending a device erase command to the signal receiving circuit.

9. The method according to claim 7 , wherein the pulse width of the device erase pulse is 0.5 seconds to 5 seconds.

10. The method according to claim 7 , wherein the device erase pulse magnitude is between 20 volts 30 volts.

11. The method according to claim 7 , wherein the device erase pulse is a single erase pulse.

12. The method according to claim 7 , wherein the control unit receives a device erase command and the control unit decodes the device erase command.