IP Library Granted Patent US 10,635,525
Granted Patent B2
US 10,635,525 · App. 15/858,393 · Granted Apr 28, 2020

Data storage devices and methods for rebuilding a memory address mapping table

Inventors: Ching-Ke Chen (Zhubei, TW); Tsu-Jung Chiang (New Taipei, TW)
Assignee: Silicon Motion, Inc.
G06F11/1016G06F11/1068G06F11/14G06F11/1458G06F12/0246G06F2212/7201G06F2212/7202
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,635,525
App. No.
15/858,393
Granted
Apr 28, 2020
Kind
B2
Abstract

A data storage device including a non-volatile memory and a micro-controller is provided. The non-volatile memory includes a plurality of data blocks. The micro-controller selects one of the data blocks as a source block and another one of the data blocks as a destination block. Also, the micro-controller duplicates data in the source block to the destination block, and when the data is corrupted and unrecoverable, stores an unrecoverable-error bit corresponding to the data into the destination block.

Claims (17)

1. A data storage device, comprising:

a flash memory, comprising a plurality of data blocks; and

a micro-controller, configured to read a respective physical-to-logical address mapping table comprising an unrecoverable-error bit from each of the data blocks in the flash memory, and build a logical-to-physical address mapping table comprising the unrecoverable-error bits according to the physical-to-logical address mapping tables in an order of precedence;

wherein the order of precedence is determined according to a respective timestamp of each of the data blocks.

2. The data storage device as claimed in claim 1 , wherein the order of precedence is determined according to a link list of the data blocks.

3. The data storage device as claimed in claim 1 , wherein the physical-to-logical address mapping tables are stored in a plurality of End-Of-Blocks (EOBs) of the data blocks.

4. A method for a data storage device to rebuild a memory address mapping table, comprising:

providing a non-volatile memory in the data storage device, which comprises at least one system information block and at least one data block in the data storage device; and

when a logical-to-physical address mapping table in the system information block is corrupted, reading an unrecoverable-error bit from a physical-to-logical address mapping table in the data block or a spare area of a data page in the data block, to rebuild the logical-to-physical address mapping table.

5. The method as claimed in claim 4 , further comprising:

when writing data to the data block, reading the unrecoverable-error bit from the logical-to-physical address mapping table and storing the unrecoverable-error bit in the physical-to-logical address mapping table or the spare area of the data page.

6. The method as claimed in claim 4 , further comprising:

in response to an error occurring when reading data from the data block, performing a recovery procedure to recover the data being read from the data block; and

in response to the recovery procedure failing, setting the unrecoverable-error bit in the logical-to-physical address mapping table to true.

7. The method as claimed in claim 4 , wherein the logical-to-physical address mapping table comprises information concerning mapping of logical addresses used by a host to physical addresses in the non-volatile memory, and the physical-to-logical address mapping table comprises information concerning mapping of the physical addresses in the non-volatile memory to the logical addresses used by a host.

8. The method as claimed in claim 4 , wherein the physical-to-logical address mapping table is stored in an End-Of-Block (EOB) of the data block.

9. The method as claimed in claim 4 , wherein the spare area of the data page further stores metadata of the data page in the data block.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 29, 2017
From: CHEN, CHING-KE; CHIANG, TSU-JUNG
To: SILICON MOTION, INC.
Reel/Frame 044506/0586 →
Priority Claims (1)
TW 106113731 A · Apr 25, 2017 · national
Continuity (1)
Related Publication 20180307558A1 · Oct 25, 2018