IP Library › Granted Patent US 10,818,774
Granted Patent B2
US 10,818,774 · App. 15/859,418 · Granted Oct 27, 2020

Plugs for interconnect lines for advanced integrated circuit structure fabrication

Inventors: Andrew W. Yeoh (Portland, OR); Ilsup Jin (Hillsboro, OR); Angelo Kandas (Portland, OR); Michael L. Hattendorf (Portland, OR); Christopher P. Auth (Portland, OR)
Assignee: Intel Corporation
H01L29/66545H01L21/02532H01L21/02636H01L21/0337H01L21/28247H01L21/28518H01L21/28568H01L21/3086H01L21/31105H01L21/31144H01L21/76224H01L21/76232H01L21/76801H01L21/76802H01L21/76816H01L21/76834H01L21/76846H01L21/76849H01L21/76877H01L21/76897H01L21/823431H01L21/823481H01L21/823807H01L21/823814H01L21/823821H01L21/823828H01L21/823842H01L21/823857H01L21/823871H01L21/823878H01L23/528H01L23/5226H01L23/5283H01L23/5329H01L23/53209H01L23/53238H01L23/53266H01L27/0207H01L27/0886H01L27/0922H01L27/0924H01L27/1104H01L28/20H01L28/24H01L29/0649H01L29/0653H01L29/0847H01L29/165H01L29/167H01L29/41783H01L29/41791H01L29/516H01L29/6653H01L29/6656H01L29/66636H01L29/66795H01L29/66818H01L29/785H01L29/7843H01L29/7845H01L29/7846H01L29/7848H01L29/7851H01L29/7854H01L21/0217H01L21/02164H01L21/0332H01L21/76883H01L21/76885H01L21/823437H01L21/823475H01L24/16H01L24/32H01L24/73H01L29/665H01L29/7842H01L29/7853H01L2224/16227H01L2224/32225H01L2224/73204
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Quick Facts
Patent No.
US 10,818,774
App. No.
15/859,418
Filed
Dec 30, 2017
Granted
Oct 27, 2020
Kind
B2
Art Unit
2822
USPC
257/368
Abstract

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes an inter-layer dielectric (ILD) layer above a substrate. A conductive interconnect line is in a trench in the ILD layer, the conductive interconnect line having a first portion and a second portion, the first portion laterally adjacent to the second portion. A dielectric plug is between and laterally adjacent to the first and second portions of the conductive interconnect line, the dielectric plug comprising a metal oxide material.

Claims (19)

1. An integrated circuit structure, comprising:

an inter-layer dielectric (ILD) layer above a substrate;

a conductive interconnect structure in a trench in the ILD layer, the conductive interconnect structure having a first conductive line and a second conductive line, an end of the first conductive line laterally spaced apart and electrically isolated from an end of the second conductive line, wherein the first and second conductive lines of the conductive interconnect structure have a bottom on the ILD layer; and

a dielectric plug between and in lateral contact with the ends of the first and second conductive lines of the conductive interconnect structure, the dielectric plug comprising a metal oxide material, the dielectric plug having a different composition than the ILD layer, wherein the dielectric plug has a bottom on the ILD layer, the bottom of the dielectric plug substantially co-planar with the bottom of the first and second conductive lines of the conductive interconnect structure.

2. The integrated circuit structure of claim 1 , wherein the metal oxide material is aluminum oxide.

3. The integrated circuit structure of claim 1 , wherein the dielectric plug has an approximately vertical seam spaced approximately equally from the first conductive line of the conductive interconnect structure and from the second conductive line of the conductive interconnect structure.

4. The integrated circuit structure of claim 1 , further comprising:

a first conductive via in a second trench in the ILD layer, the first conductive via below the bottom of the first conductive line, and the first conductive via electrically coupled to the first conductive line; and

a second conductive via in a third trench in the ILD layer, the second conductive via below the bottom of the second conductive line, and the second conductive via electrically coupled to the second conductive line.

5. The integrated circuit structure of claim 1 , wherein the first and second conductive lines of the conductive interconnect structure comprise a conductive barrier liner and a conductive fill material, the conductive fill material comprising cobalt.

6. An integrated circuit structure, comprising:

a first plurality of conductive interconnect structures in and spaced apart by a first inter-layer dielectric (ILD) layer above a substrate, wherein individual ones of the first plurality of conductive interconnect structures have a dielectric plug in lateral contact with and electrically isolating corresponding ends of conductive lines, wherein the conductive lines have a bottom on the first ILD layer, the dielectric plug having a bottom on the first ILD layer, the bottom of the dielectric plug substantially co-planar with the bottom of the conductive lines, and the dielectric plug comprising a metal oxide material, the dielectric plug having a composition different than the first ILD layer; and

a second plurality of conductive interconnect structures in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect structures have conductive lines having ends separated by the second ILD layer.

7. The integrated circuit structure of claim 6 , wherein the metal oxide material is aluminum oxide.

8. The integrated circuit structure of claim 7 , wherein the first ILD layer and the second ILD layer comprise a carbon-doped silicon oxide material.

9. The integrated circuit structure of claim 6 , wherein the conductive lines of the the first plurality of conductive interconnect structures comprise a first conductive barrier liner and a first conductive fill material, the second plurality of conductive interconnect structures comprise a second conductive barrier liner and a second conductive fill material, and wherein the first conductive fill material is different in composition from the second conductive fill material.

10. The integrated circuit structure of claim 9 , wherein the first conductive fill material comprises cobalt, and the second conductive fill material comprises copper.

11. The integrated circuit structure of claim 6 , wherein the conductive lines of the first plurality of conductive interconnect structures have a first pitch, the conductive lines of the second plurality of conductive interconnect structures have a second pitch, and wherein the second pitch is greater than the first pitch.

12. The integrated circuit structure of claim 6 , wherein the conductive lines of the the first plurality of conductive interconnect structures have a first width, the conductive lines of the the second plurality of conductive interconnect structures have a second width, and wherein the second width is greater than the first width.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 9, 2018
From: YEOH, ANDREW W.; JIN, ILSUP; KANDAS, ANGELO; HATTENDORF, MICHAEL L.; AUTH, CHRISTOPHER P.
To: INTEL CORPORATION
Reel/Frame 045156/0300 →
Continuity (2)
Provisional Application 62593149 · Nov 30, 2017
Related Publication 20190164814A1 · May 30, 2019