Method and system for acquisition of test data

1. A tester system, said system comprising:

a controller processor;

a plurality of programmable accelerator circuits coupled to and controlled by said controller processor, said plurality of programmable accelerator circuits for providing input test signals and for capturing output test signals; and

a plurality of load boards respectively coupled to said plurality of programmable accelerator circuits, said plurality of load boards for applying said input test signals to a plurality of devices under test (DUTs) and for capturing said output test signals therefrom, wherein each of said plurality of load boards comprises:

a first set of connections for transmitting input test signals to a respective one of said plurality of DUTs;

a second set of connections for receiving output test signals from said respective one of said plurality of DUTs; and

sideband connectors for receiving sideband information, including test related information from said respective one of said plurality of DUTs, wherein said test related information is operable to be used for debug purposes, and wherein further, said sideband information is received from said respective one of said plurality of DUTs at least in partial coincidence with receiving said output test signals from said respective one of said plurality of DUTs, wherein said first set of connections, said second set of connections and said sideband connectors are operable to physically and electrically couple to input/output pins of said respective one of said plurality of DUTs.

2. The tester system of claim 1 , wherein said plurality of load boards is operable for receiving, in parallel, a plurality of respective test related information from said plurality of DUTs and further comprising a memory coupled to said controller processor, wherein said memory is operable to receive and store said plurality of respective test related information.

3. The tester system of claim 2 , wherein said controller processor is a central processing unit (CPU).

4. The tester system of claim 1 , wherein a content of said test related information is programmable and customer specific.

5. The tester system of claim 1 , wherein each of said plurality of programmable accelerator circuits comprises a field programmable gate array circuit.

6. The tester system of claim 1 , wherein said test related information of said respective one of said plurality of DUTs is operable to be captured and stored in synchronization with input and output test signals of a test program testing said respective one of said plurality of DUTs.

7. The tester system of claim 1 , wherein said sideband information is collected in real time.

8. The tester system of claim 1 , wherein independent debug operations and sideband information collection are performed independently and at least in partial coincidence on said plurality of DUTs.

9. The tester system of claim 1 , wherein said sideband information includes debug related information, wherein said sideband connectors communicate said debug related information and said plurality of programmable accelerator circuits perform debug analysis.

10. The tester system of claim 1 , wherein said sideband connectors enable communication of debug information without coupling additional dedicated external wiring harnesses.

11. The tester system of claim 1 , wherein said sideband connectors enable debug information to be captured on-the-fly during persistent testing time frames.

12. The tester system of claim 1 , wherein testing of said DUTs includes persistent testing and a portion of said persistent testing performed on said respective one of said plurality of DUTs is performed at least in partial coincidence with another portion of said persistent testing performed on another respective one of said plurality of DUTs, wherein said plurality of programmable accelerator circuits include respective persistent test signal interfaces that communicate respective persistent testing information.

13. The tester system of claim 1 , wherein testing of said DUTs includes persistent testing, wherein persistent testing information and debug related information associated with said respective one of said plurality of DUTs are coordinated.

14. The tester system of claim 1 , wherein said sideband connectors enable debug information to be captured at least in partial coincidence with performing persistent testing operations.

15. The tester system of claim 1 , wherein said plurality of programmable accelerator circuits are configured to:

perform preliminary analysis of persistent test information; and

reconfiguration of debug information and said persistent test information for communication to an external device.

16. The tester system of claim 1 , wherein said sideband connectors are operable to communicate information associated with monitoring activities and traffic inside said respective one of said plurality of DUTs.

17. The tester system of claim 1 , wherein said sideband connectors are compatible with a protocol selected from said group comprising a Joint Test Action Group (JTAG) standards, a Universal Asynchronous Receiver-Transmitter (UART) protocol, a Inter-Integrated Circuit Bus (I2C) protocol, and a Universal Serial Bus (USB) protocol.

18. The tester system of claim 1 , wherein said plurality of programmable accelerator circuits include Field Programmable Gate Arrays (FPGAs).