IP Library Granted Patent US 10,069,009
Granted Patent B2
US 10,069,009 · App. 15/861,700 · Granted Sep 4, 2018

Method for forming recess within epitaxial layer

Inventors: An-Chi Liu (Tainan, TW); Chun-Hsien Lin (Tainan, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L29/7848H01L21/283H01L21/7684H01L21/76805H01L21/76846H01L21/76895H01L23/535H01L23/53266H01L29/0847H01L29/161H01L29/1608H01L29/24H01L29/267H01L29/41766H01L29/665H01L29/6659H01L29/66636H01L29/7834H01L29/7845H01L29/165H01L29/66545
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Quick Facts
Patent No.
US 10,069,009
App. No.
15/861,700
Granted
Sep 4, 2018
Kind
B2
Abstract

A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first recess adjacent to two sides of the gate structure; forming an epitaxial layer in the first recess; removing part of the epitaxial layer to forma second recess; and forming an interlayer dielectric (ILD) layer on the gate structure and into the second recess.

Claims (33)

1. A method for fabricating semiconductor device, comprising:

forming a gate structure on a substrate;

forming a first recess adjacent to two sides of the gate structure;

forming an epitaxial layer in the first recess;

removing part of the epitaxial layer to form a second recess; and

after removing part of the epitaxial layer to form the second recess forming an interlayer dielectric (ILD) layer on the gate structure and into the second recess.

2. The method of claim 1 , further comprising:

forming a spacer adjacent to the gate structure;

forming the first recess adjacent to the spacer;

forming the epitaxial layer;

forming the second recess in the epitaxial layer;

forming a contact etch stop layer (CESL) on the gate structure and in the second recess;

forming the ILD layer on the CESL;

planarizing part of the ILD layer; and

transforming the gate structure into a metal gate.

3. The method of claim 2 , further comprising:

forming a hard mask on the metal gate;

removing part of the ILD layer to form a first contact hole on the epitaxial layer;

removing part of the ILD layer to form a second contact hole on the hard mask; and

removing part of the CESL and part of the hard mask at the same time.

4. The method of claim 3 , further comprising:

forming a first stress layer in the first contact hole and the second contact hole;

forming a second stress layer in the first contact hole and the second contact hole;

planarizing part of the first stress layer and part of the second stress layer to form a first contact plug and a second contact plug.

5. The method of claim 4 , wherein the first stress layer comprises Ti.

6. The method of claim 4 , wherein the second stress layer comprises W.

7. The method of claim 1 , further comprising:

performing a first etching process to form the first recess;

forming the epitaxial layer in the first recess; and

performing a second etching process to form the second recess.

8. The method of claim 7 , wherein the second etching process comprises a lateral etching process.

9. The method of claim 1 , wherein the first recess comprises a hexagon.

10. The method of claim 1 , wherein the second recess comprises a hexagon or a rectangle.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2021
From: UNITED MICROELECTRONICS CORPORATION
To: MARLIN SEMICONDUCTOR LIMITED
Reel/Frame 056991/0292 →
Priority Claims (1)
TW 105141215 A · Dec 13, 2016 · national
Continuity (2)
Division 15401092 · Jan 8, 2017
Related Publication 20180166571A1 · Jun 14, 2018