Integrated circuit with a fin and gate structure and method making the same

1. A semiconductor structure comprising:

a first device fin and a second device fin formed on a substrate;

fill fins formed on the substrate, wherein the fill fins are dielectric features and include a first fill fin and a second fill fin, the second fill fin being disposed between the first and second device fins, the second fill fin is spaced away from the first and second device fins, the second fill fin including a first dielectric material layer and a second dielectric material layer deposited on the first dielectric material layer, wherein the first and second dielectric material layers are different from each other in composition; and

a gate stack formed on the first and second device fins and the first and second fill fins, wherein a portion of the gate stack is inserted in a gap between the first device fin and the second fill fin, wherein

the first fill fin includes a first width and the second fill fin includes a second width greater than the first width;

the first fill fin includes the first dielectric material layer and is free of the second dielectric material layer; and

the second fill fin includes both the first and second dielectric material layers.

2. The semiconductor structure of claim 1 , wherein

the first dielectric material layer includes a high-k dielectric material; and

the second dielectric material layer includes a carbon-containing material.

3. The semiconductor structure of claim 2 , wherein

the first dielectric material layer is chosen from a metal oxide, a metal nitride and a combination thereof; and

the second dielectric material layer includes carbon and silicon.

4. The semiconductor structure of claim 3 , wherein

the first dielectric material layer includes at least one of hafnium oxide (H f O 2 ), zirconium oxide (Z r O 2 ), and aluminum oxide (Al 2 O 3 ); and

the second dielectric material layer includes one of silicon carbon oxide, silicon carbon oxynitride, and silicon carbon nitride.

5. The semiconductor structure of claim 1 , further comprising a third fill fin, wherein

the third fill fin includes a third width that is greater than the first width and less than the second width; and

the third fill fin includes the first dielectric material layer and is free of the second dielectric material layer.

6. The semiconductor structure of claim 5 , further comprising a fourth fill fin, wherein

the device fins are oriented in a first direction;

the gate stack is oriented in a second direction being orthogonal to the first direction;

the first, second and third fill fins are oriented in the first direction;

the fourth fill fin is oriented in the second direction.

7. The semiconductor structure of claim 6 , wherein

the fourth fill fin has a fourth width greater than the second width; and

the fourth fill fin includes both the first and second dielectric material layers.

8. The semiconductor structure of claim 1 , wherein

the first dielectric material layer includes hafnium oxide; and

the second dielectric material layer includes silicon carbon oxide.

9. The semiconductor structure of claim 1 , wherein

the gate stack includes a gate dielectric feature and a gate electrode disposed on the gate dielectric feature; and

the gate dielectric feature includes a high-k dielectric material and the gate electrode includes one of metal and metal alloy.

10. The semiconductor structure of claim 9 , wherein the first and second device fins include a semiconductor material chosen from silicon, silicon germanium and silicon germanium.

11. The semiconductor structure of claim 10 , further comprising source/drain features formed on the first device fin and disposed on both sides of the gate stack, wherein the first device fin, the gate stack and the source/drain features are configured to form a fin field-effect transistor (FinFET).

12. A method for fabricating an integrated circuit, comprising:

forming a device fin structure on a substrate, wherein the device fin structure includes a plurality of device fins with trenches defined among the device fins;

filling the trenches with a first dielectric material layer and a second dielectric material layer on the first dielectric material layer;

selectively removing upper portions of the first dielectric material layer, resulting in a first fill fin and a second fill fin being spaced away from two adjacent devices fins of the device fins with gaps defined therein; and

forming a gate stack on the device fins and the at least one fill fin with portions of the gate stack inserted in the gaps, wherein

the first fill fin includes a first width and the second fill fin includes a second width greater than the first width;

the first fill fin includes the first dielectric material layer and is free of the second dielectric material layer;

the second fill fin includes both the first and second dielectric material layers; and

the first and second dielectric material layers are different from each other in composition.

13. The method of claim 12 , wherein the filling of the trenches includes

performing an atomic layer deposition (ALD) process to deposit the first dielectric material layer in the trenches; and

depositing the second dielectric layer on the first dielectric material layer to fill in the trenches, using one of spin-on coating and flowable chemical vapor deposition (FCVD).

14. The method of claim 13 , further comprising a chemical mechanical polishing (CMP) process to the second dielectric material layer after the depositing of the second dielectric material layer.

15. The method of claim 13 , wherein

the first dielectric material layer includes a high-k dielectric material; and

the second dielectric material layer includes a carbon-containing material.

16. The method of claim 15 , wherein

the first dielectric material layer is chosen from a metal oxide, a metal nitride and a combination thereof; and

the second dielectric material layer includes carbon and silicon.

17. The method of claim 15 , wherein

the first dielectric material layer includes at least one of hafnium oxide (H f O 2 ), zirconium oxide (Z r O 2 ), and aluminum oxide (Al 2 O 3 ); and

the second dielectric material layer includes one of silicon carbon oxide, silicon carbon oxynitride, and silicon carbon nitride.

18. The method of claim 13 , wherein

the trenches include a first trench having a first width and a second trench having a second width greater than the first width;

the performing of the ALD process to deposit the first dielectric material layer includes depositing the first dielectric material layer to completely fill the first trench; and

the depositing of the second dielectric layer on the first dielectric material layer to fill in the trenches includes depositing the second dielectric material layer in the second trench, wherein the second dielectric material layer is free from the first trench.

19. A semiconductor structure comprising:

a first device fin and a second device fin formed on a substrate;

a first dielectric fin formed on the substrate and disposed between the first and second the device fins;

a second dielectric fin formed on the substrate and disposed on a side of the second device fin opposite to the first device fin; and

a gate stack disposed on the first and second device fins and the dielectric fin, wherein a first portion of the gate stack is inserted in a first gap between the first device fin and the dielectric fin, and a second portion of the gate stack is inserted in a second gap between the second device fin and the dielectric fin, wherein

the first dielectric fin includes a first width and the second dielectric fin includes a second width greater than the first width;

the first dielectric fin includes a first dielectric material layer and is free of a second dielectric material layer;

the second dielectric fin includes both the first and second dielectric material layers; and

the first and second dielectric material layers are different from each other in composition.

20. The semiconductor structure of claim 19 , further comprising a third dielectric fin, wherein

the third dielectric fin includes a third width that is greater than the first width and less than the second width; and

the third dielectric fin includes the first dielectric material layer and is free of the second dielectric material layer.