IP Library › Granted Patent US 10,419,227
Granted Patent B2
US 10,419,227 · App. 15/865,007 · Granted Sep 17, 2019

Network card

Inventors: Sean David Large (Bothell, WA); Douglas D. Barga (Bellevue, WA)
Assignee: ALLIED TELESIS HOLDINGS KABUSHIKI KAISHA
H04L12/12G06F13/4068G06F13/4286H04L49/15H04L49/30G06F2213/0026H04B10/40Y02D50/40Y02D50/42
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Quick Facts
Patent No.
US 10,419,227
App. No.
15/865,007
Granted
Sep 17, 2019
Kind
B2
Abstract

A network interface controller (NIC), comprising: a Gigabit Fiber Transceiver; a Gigabit Ethernet Controller; a Gigabit Ethernet Switch; and a microprocessor unit (MPU), where the MPU initializes the Gigabit Ethernet Switch to pass Ethernet packets unmolested between the Gigabit Fiber Transceiver and the Gigabit Ethernet Controller, where the Gigabit Ethernet Switch maintains a link between the Gigabit Ethernet Controller and the Gigabit Fiber Transceiver whether or not a link speed between the Gigabit Ethernet Switch and the Gigabit Fiber Transceiver matches a link speed between the Gigabit Ethernet Switch and the Gigabit Ethernet Controller, where the MPU configures the Gigabit Ethernet Switch to match a link speed between the Gigabit Ethernet Switch and the Gigabit Fiber Transceiver with a link speed between the Gigabit Ethernet Switch and the Gigabit Ethernet Controller during normal operation, and where the Gigabit Ethernet Controller can respond to a Wake on LAN (WoL) request from a network.

Claims (42)

1. A method comprising:

resetting, by a microprocessor unit (MPU) in communication with a Gigabit Ethernet Switch via a serial management interface (SMI), all of the Gigabit Ethernet Switch settings to default;

disabling, by the MPU, a port linking the Gigabit Ethernet Switch and a Gigabit Ethernet Controller causing a PC connected to the Gigabit Ethernet Controller to indicate no link;

reading, by the MPU, a board ID to determine a type of optic installed; and

determining, by the MPU in communication with a small form-factor pluggable (SFP) cage via an inter-integrated circuit (I 2 C) link, if an SFP module is installed;

wherein if the SFP module is installed, further comprising:

determining, by the MPU, a type of the installed SFP module;

setting, by the MPU, a port of the Gigabit Ethernet Switch linking the Gigabit Ethernet Switch and the SFP Cage to a 100-FX mode if the determined type of the installed SFP module is 100-FX type; and

setting, by the MPU, the port of the Gigabit Ethernet Switch linking the Gigabit Ethernet Switch and the SFP Cage to a 1000-X mode if the determined type of the installed SFP module is 1000-X type.

2. The method of claim 1 , further comprising:

determining, by the MPU, a fiber link status.

3. A system comprising:

a network interface controller (NIC), comprising:

a small form-factor pluggable (SFP) Cage;

an SFP Module, wherein the SFP Cage is configured to receive the SFP Module;

a PCIe slot on a PC motherboard of a PC, wherein the PCIe slot is configured to receive the NIC;

a Gigabit Ethernet Controller;

a Gigabit Ethernet Switch; and

a microprocessor unit (MPU);

wherein the Gigabit Ethernet Switch maintains a link between the Gigabit Ethernet Controller and the SFP Cage whether or not a link speed between the Gigabit Ethernet Switch and the SFP Cage matches a link speed between the Gigabit Ethernet Switch and the Gigabit Ethernet Controller;

wherein the MPU configures the Gigabit Ethernet Switch to match the link speed between the Gigabit Ethernet Switch and the SFP Cage with the link speed between the Gigabit Ethernet Switch and the Gigabit Ethernet Controller during normal operation;

wherein the Gigabit Ethernet Controller can respond to a Wake on LAN (WoL) request from a network; and

wherein the MPU is further configured to detect a link down on a first port of the Gigabit Ethernet Switch connected to the SFP Cage, and wherein the MPU is further configured to pass a status of the link down to a second port of the Gigabit Ethernet Switch connected to the Gigabit Ethernet Controller, wherein the PC receives the status as a loss of fiber link.

4. The system of claim 3 , wherein the MPU is further configured to read the SFP module speed via an inter-integrated circuit (I 2 C) link between the MPU and the SFP cage when the SFP Module is detachably attached to the SFP Cage.

5. The system of claim 3 , wherein the link speed between the Gigabit Ethernet Switch and the Gigabit Ethernet Controller when the PC is active is one of: 1000-T and 100-TX.

6. The system of claim 3 , wherein the WoL request from the network is received at the Gigabit Ethernet Controller.

7. A system comprising:

a network interface controller (NIC), comprising:

a small form-factor pluggable (SFP) Cage;

an SFP Module, wherein the SFP Cage is configured to receive the SFP Module;

a PCIe slot on a PC motherboard of a PC, wherein the PCIe slot is configured to receive the NIC;

a Gigabit Ethernet Controller;

a Gigabit Ethernet Switch; and

a microprocessor unit (MPU);

wherein the Gigabit Ethernet Switch maintains a link between the Gigabit Ethernet Controller and the SFP Cage whether or not a link speed between the Gigabit Ethernet Switch and the SFP Cage matches a link speed between the Gigabit Ethernet Switch and the Gigabit Ethernet Controller;

wherein the MPU configures the Gigabit Ethernet Switch to match the link speed between the Gigabit Ethernet Switch and the SFP Cage with the link speed between the Gigabit Ethernet Switch and the Gigabit Ethernet Controller during normal operation;

wherein the Gigabit Ethernet Controller can respond to a Wake on LAN (WoL) request from a network; and

wherein a first port of the Gigabit Ethernet Switch connected to the SFP Cage is set at a constant link speed, wherein a second port of the Gigabit Ethernet Switch connected to the Gigabit Ethernet Controller is set to auto-negotiate to a highest possible link speed, and wherein the Gigabit Ethernet Controller enters a low power mode when the PC is turned off, and wherein the WoL request from the network is received at the Gigabit Ethernet Controller.

8. The system of claim 7 , wherein the MPU is further configured to read the SFP module speed via an inter-integrated circuit (I2C) link between the MPU and the SFP cage when the SFP Module is detachably attached to the SFP Cage.

9. The system of claim 7 , wherein the link speed between the Gigabit Ethernet Switch and the Gigabit Ethernet Controller when the PC is active is one of: 1000-T and 100-TX.

10. The system of claim 7 , wherein a second port of the Gigabit Ethernet Switch connected to the SFP Cage is set to auto-negotiate to a highest possible link speed, and wherein the Gigabit Ethernet Controller enters a low power mode when the PC is turned off.

11. The system of claim 7 , wherein the WoL request from the network is received at the Gigabit Ethernet Controller.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 23, 2018
From: LARGE, SEAN DAVID; BARGA, DOUGLAS D
To: ALLIED TELESIS HOLDINGS KABUSHIKI KAISHA; ALLIED TELESIS HOLDINGS K.K.; ALLIED TELESIS, INC.
Reel/Frame 044702/0023 →
Continuity (3)
Provisional Application 62444170 · Jan 9, 2017
Provisional Application 62448838 · Jan 20, 2017
Related Publication 20180198633A1 · Jul 12, 2018
Cited By (2)
US 12,671,922 US 12,738,959