IP Library › Granted Patent US 10,580,777
Granted Patent B2
US 10,580,777 · App. 15/865,710 · Granted Mar 3, 2020

Semiconductor device and method for fabricating the same

Inventors: Jeong-Yeop Lee (Gyeonggi-do, KR); Dong-Su Park (Gyeonggi-do, KR); Jong-Bum Park (Seoul, KR); Sang-Do Lee (Gyeonggi-do, KR); Jae-Min Lee (Seoul, KR); Kee-Jeung Lee (Seoul, KR); Jun-Soo Jang (Chungcheongbuk-do, KR)
Assignee: SK hynix Inc.
H01L27/10855H01L27/10814H01L27/10852H01L27/10876H01L27/10894H01L28/75H01L28/91H01L28/92
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,580,777
App. No.
15/865,710
Granted
Mar 3, 2020
Kind
B2
Abstract

A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.

Claims (31)

1. A method for fabricating a semiconductor device, comprising:

forming a mold stack pattern including a plurality of openings over a substrate and including a mold layer and a supporter layer which are stacked;

forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer;

forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer;

forming a supporter by etching the supporter layer exposed by the electrode cutting portion using the barrier portion as an etch barrier;

selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and

removing the mold layer.

2. The method of claim 1 , wherein a bottom surface of the electrode cutting portion has a depth that partially covers the filler portion.

3. The method of claim 1 , wherein the forming of the bottom electrode layer includes:

conformally forming a first bottom electrode layer over the plurality of the openings and the supporter layer in such a manner that a gap is defined inside each of the plurality of the openings; and

forming a second bottom electrode layer filling the gap over the first bottom electrode layer.

4. The method of claim 3 , wherein the second bottom electrode layer includes a material having an etch selectivity with respect to the supporter layer.

5. The method of claim 3 , wherein the second bottom electrode layer includes polysilicon.

6. The method of claim 3 , wherein the first bottom electrode layer includes a metal or a metal nitride.

7. The method of claim 3 , wherein the selective removing of the barrier portion to form the hybrid pillar-type bottom electrode includes:

performing an etch-back process by making the first bottom electrode layer and the second bottom electrode layer have different selectivities.

8. The method of claim 1 , wherein the forming of the bottom electrode layer includes:

conformally forming a first bottom electrode layer over the plurality of the openings and the supporter layer in such a manner that a gap is defined inside each of the plurality of the openings;

removing the first bottom electrode layer from an upper surface of the supporter layer to form a cylindrical first bottom electrode which is disposed inside each of the plurality of the openings; and

forming a second bottom electrode layer filling the gap over the cylindrical first bottom electrode.

9. The method of claim 1 , wherein the forming of the filler portion disposed inside the plurality of the openings, the barrier portion extended upwardly from the filler portion, and the electrode cutting portion exposing the surface of the supporter layer by selectively etching the bottom electrode layer includes;

forming a supporter mask layer over the bottom electrode layer; and

etching the bottom electrode layer by using the supporter mask layer as an etch barrier,

wherein a bottom surface of the electrode cutting portion has a depth that partially covers the filler portion.

10. The method of claim 1 , further comprising:

forming a dielectric layer over the hybrid pillar-type bottom electrode and the supporter, after the removing of the mold layer; and

forming a top electrode over the dielectric layer.

11. The method of claim 1 , further comprising:

forming a pillar-type bottom electrode and a cylindrical bottom electrode over the pillar-type bottom electrode by recessing inside of the hybrid pillar-type bottom electrode, after the removing of the mold layer.

12. The method of claim 3 , wherein the gap inside each of the openings consists of an upper gap, an intermediate gap and a lower gap, wherein the intermediate and lower gaps have a first width and the upper gap has a second width that is wider than the first width.

13. The method of claim 12 , wherein the first width is from approximately 100 Å to approximately 400 Å.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 25, 2018
From: JANG, JUN-SOO
To: SK HYNIX INC.
Reel/Frame 047148/0305 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 9, 2018
From: LEE, JEONG-YEOP; PARK, DONG-SU; PARK, JONG-BUM; LEE, SANG-DO; LEE, JAE-MIN; LEE, KEE-JEUNG
To: SK HYNIX INC.
Reel/Frame 045028/0380 →
Priority Claims (1)
KR 10-2017-0049286 · Apr 17, 2017 · national
Continuity (1)
Related Publication 20180301457A1 · Oct 18, 2018
Cited By (1)
US 12,543,330