Transistor display panel including a transistor and an overlapping region of a gate line and data line
A transistor display panel includes a substrate, a gate line disposed on the substrate, a data line disposed on the substrate, and a transistor disposed on the substrate. The transistor includes a first electrode, a second electrode overlapping the first electrode, a semiconductor layer disposed between the first electrode and the second electrode, and a gate electrode. The semiconductor layer is disposed in an overlapping region where the gate line and the data line overlap each other.
1. A transistor display panel comprising:
a substrate;
a gate line disposed on the substrate;
a data line disposed on the substrate; and
a transistor disposed on the substrate,
wherein the transistor includes:
a first electrode;
a second electrode overlapping the first electrode;
a semiconductor layer disposed between the first electrode and the second electrode; and
a gate electrode, wherein the semiconductor layer is disposed in an overlapping region where the gate line and the data line overlap each other.
2. The transistor display panel of claim 1 , wherein the gate electrode surrounds at least a portion of the semiconductor layer.
3. The transistor display panel of claim 2 , wherein the gate line includes a hole, and the semiconductor layer is disposed within the hole.
4. The transistor display panel of claim 3 , wherein the hole overlaps the data line.
5. The transistor display panel of claim 1 , wherein the first electrode is a part of the data line, and the gate electrode is a part of the gate line.
6. The transistor display panel of claim 5 , wherein the first electrode is aligned in parallel with the data line, and the gate electrode is aligned in parallel with the gate line.
7. The transistor display panel of claim 1 , further comprising:
a first insulating layer disposed between the first electrode and the gate electrode; and
a second insulating layer disposed between the gate electrode and the semiconductor layer,
wherein the semiconductor layer is connected with the first electrode through a first contact hole formed in the first and second insulating layers.
8. The transistor display panel of claim 7 , wherein the gate line includes a hole that surrounds the first contact hole, and the semiconductor layer is disposed within the first contact hole.
9. The transistor display panel of claim 8 , wherein the second insulating layer overlaps the gate electrode.
10. The transistor display panel of claim 8 , wherein the semiconductor layer has a column shape.
11. The transistor display panel of claim 7 , further comprising
an insulator disposed between the first insulating layer and the gate line.
12. The transistor display panel of claim 1 , further comprising
a pixel electrode electrically connected to the transistor.
13. The transistor display panel of claim 12 , further comprising
an insulating layer disposed between the second electrode and the pixel electrode,
wherein the pixel electrode includes an extension connected with the second electrode through a second contact hole formed in the insulating layer.
14. The transistor display panel of claim 1 , further comprising:
a first insulating layer disposed between the first electrode and the gate electrode;
a second insulating layer disposed between the gate electrode and the semiconductor layer; and
a third insulating layer disposed on the semiconductor layer,
wherein the semiconductor layer is connected with the first electrode through a first contact hole formed in the first and second insulating layers, and the second electrode is connected with the semiconductor layer through a second contact hole formed in the third insulating layer.
15. The transistor display panel of claim 14 , wherein the second contact hole overlaps the first contact hole.
16. The transistor display panel of claim 14 , wherein the semiconductor layer includes a central portion and a peripheral portion extending away from the central portion, wherein the central portion has an incline and the peripheral portion is substantially horizontal, and the second contact hole overlaps the peripheral portion, but does not overlap the central portion.
17. The transistor display panel of claim 1 , wherein at least a part of each of the first electrode, the gate electrode, and the second electrode is disposed in the overlapping region.
18. The transistor display panel of claim 1 , wherein the first electrode receives a data signal from the data line, and the gate electrode receives a gate signal from the gate line.