Conversion apparatus, imaging apparatus, electronic apparatus, and conversion method
The present technology relates to a conversion apparatus, an imaging apparatus, an electronic apparatus, and a conversion method that are capable of reducing the scale of a circuit. The conversion apparatus includes: a comparison unit that compares an input voltage of an input signal and a ramp voltage of a ramp signal that varies with time; and a storage unit that holds a code value when a comparison result from the comparison unit is inverted, the holding of the code value by the storage unit being repeated a plurality of times, to generate a digital signal having a predetermined bit number. The predetermined bit number is divided into high-order bits and low-order bits, the low-order bits are acquired earlier than the high-order bits, and the acquired low-order bits and the high-order bits are combined with each other, to generate the digital signal having the predetermined bit number. The present technology can be applied to a portion of an image sensor, in which AD conversion is performed.
1. An imaging apparatus, comprising:
an upper substrate including a plurality of pixel blocks; and
a lower substrate connected to the upper substrate by Cu—Cu bonding and including a plurality of A/D convertors arranged in a matrix,
wherein each of the A/D convertors includes a comparator and a latch circuit,
wherein the comparator is configured to compare an analog signal conveyed from one of the pixel blocks via the Cu—Cu bonding and a reference signal conveyed from a D/A Converter,
wherein the latch circuit is configured to receive an output signal of the comparator and generate a digital signal, and
wherein a load MOS is provided in the lower substrate and connected to an input terminal of each of the A/D convertors.
2. The imaging apparatus according to claim 1 , wherein the reference signal is a ramp signal that varies with time.
3. The imaging apparatus according to claim 1 , wherein the latch circuit is configured to hold a code value when the output signal of the comparator is inverted.
4. The imaging apparatus according to claim 1 , wherein the digital signal has a predetermined bit number.
5. The imaging apparatus according to claim 4 , wherein the predetermined bit number is divided into high-order bits and low-order bits.
6. The imaging apparatus according to claim 5 , wherein the low-order bits are acquired earlier than the high-order bits, and the acquired low-order bits and the high-order bits are combined with each other.
7. The imaging apparatus according to claim 5 , wherein the low-order bits are Gray codes.
8. The imaging apparatus according to claim 5 , wherein at least one bit of the low-order bits and the high-order bits is shared.
9. The imaging apparatus according to claim 8 , wherein the digital signal is corrected by a value of a bit that is one-order lower than the shared bit.
10. The imaging apparatus according to claim 5 , wherein the ramp signal for acquiring the low-order bits and the ramp signal for acquiring the high-order bits have different cycles.