Semiconductor storage device

1. A semiconductor storage device comprising:

a substrate;

a plurality of word lines provided at different positions along a first direction intersecting a surface of the substrate and extending in a second direction parallel to the surface of the substrate; and

a NAND string provided above the substrate and extending in the first direction including:

a first memory cell transistor connected to a first word line of the word lines and provided at an intersection between the first word line and the NAND string;

a second memory cell transistor connected to a second word line of the word lines, provided at an intersection between the second word line and the NAND string, and disposed above the first memory cell transistor; and

a third memory cell transistor connected to a third word line of the word lines and provided at an intersection between the third word line and the NAND string, and disposed above the second memory cell transistor, wherein

the first memory cell transistor is provided at a lowest position among the memory cell transistors in the first direction, and

during a first program verify operation when a data item of a level is written to the first memory cell transistor, the second memory cell transistor, and the third memory cell transistor, a first verify voltage is applied to a gate of the first memory cell transistor, and a second verify voltage different from the first verify voltage is applied to gates of the second and third memory cell transistors.

2. The device of claim 1 , wherein

the NAND string further includes a fourth memory cell transistor connected to a fourth word line of the word lines, provided at an intersection between the fourth word line and the NAND string, and disposed above the third memory cell transistor, and

during a second program verify operation when the data item of the level is written to the second memory cell transistor, the third memory cell transistor, and the fourth memory cell transistor, a third verify voltage different from the second verify voltage is applied to a gate of the fourth memory cell transistor.

3. The device of claim 1 , wherein

the NAND string further includes:

a backgate transistor disposed below the first memory cell transistor,

a fifth memory cell transistor disposed in a same layer as that of the first memory cell transistor above the backgate transistor,

a sixth memory cell transistor disposed in a same layer as that of the second memory cell transistor above the fifth memory cell transistor, and

a seventh memory cell transistor disposed in a same layer as that of the third memory cell transistor above the sixth memory cell transistor, wherein

during the first program verify operation when the data item of the level is further written to the fifth memory cell transistor, the sixth memory cell transistor and the seventh memory cell transistor, the first verify voltage is applied to a gate of the fifth memory cell transistor, and the second verify voltage is applied to gates of the sixth and seventh memory cell transistors.

4. The device of claim 3 , wherein

the NAND string further includes:

a fourth memory cell transistor connected to one fourth word line of the word lines and provided at an intersection between the fourth word line and the NAND string; and

an eighth memory cell transistor disposed in a same layer as that of the fourth memory cell transistor above the seventh memory cell transistor, and

during a second program verify operation when the data item of the level is written to the second memory cell transistor, the third memory cell transistor, the fourth memory cell transistor, the sixth memory cell transistor, the seventh memory cell transistor and the eighth memory cell transistor, a third verify voltage different from the second verify voltage is applied to a gate of the fourth memory cell transistor and a gate of the eighth memory cell transistor.

5. The device of claim 1 , wherein the NAND string has a bow shape.

6. The device of claim 1 , wherein the NAND string has a tapered shape.

7. The device of claim 1 , wherein the first verify voltage is higher than the second verify voltage.

8. The device of claim 1 , wherein the first verify voltage is lower than the second verify voltage.

9. The device of claim 2 , wherein the second verify voltage is higher than the first verify voltage.

10. The device of claim 2 , wherein the third verify voltage is higher than the second verify voltage.

11. The device of claim 9 , wherein the third verify voltage is higher than the second verify voltage.

12. The device of claim 9 , wherein the third verify voltage is lower than the second verify voltage.

13. The device of claim 11 , wherein a second memory hole diameter of the second memory cell transistors is larger than a first memory hole diameter of the first memory cell transistor, a third memory hole diameter of the third memory cell transistor is larger than the second memory hole diameter of the second memory cell transistor, and a fourth memory hole diameter of the fourth memory cell transistor is larger than the third memory hole diameter of the third memory cell transistor.

14. The device of claim 2 , wherein the second verify voltage is lower than the first verify voltage.

15. The device of claim 2 , wherein the third verify voltage is higher than the second verify voltage.

16. The device of claim 1 , wherein the NAND string is electrically connected between a bit line and a source line.

17. The device of claim 14 , wherein the third verify voltage is lower than the second verify voltage.

18. The device of claim 14 , wherein the third verify voltage is higher than the second verify voltage.

19. The device of claim 17 , wherein a second memory hole diameter of the second memory cell transistor is smaller than a first memory hole diameter of the first memory cell transistor, a third diameter of the third memory cell transistor is smaller than the second memory hole of the second memory cell transistor, and a fourth memory hole diameter of the fourth memory cell transistor is smaller than the third memory hole diameter of the third memory cell transistor.

20. The device of claim 2 , wherein the fourth memory cell transistor is provided at a highest position among the memory cell transistors in the first direction and the third verify voltage applied to the fourth memory cell transistor is a highest voltage among the verify voltages applied to the memory cell transistors.

21. The device of claim 2 , wherein the fourth memory cell transistor is provided at a highest position among the memory cell transistors in the first direction and the third verify voltage applied to the fourth memory cell transistor is a lowest voltage among the verify voltages applied to the memory cell transistors.