IP Library › Granted Patent US 10,388,756
Granted Patent B2
US 10,388,756 · App. 15/869,087 · Granted Aug 20, 2019

Semiconductor device and method for fabricating the same

Inventors: Yen-Hsing Chen (Taipei, TW); Chun-Yu Chen (Taichung, TW); Chung-Ting Huang (Kaohsiung, TW); Zih-Hsuan Huang (Tainan, TW); Yu-Chien Sung (Taoyuan, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L29/66636H01L21/033H01L21/32139H01L27/0886H01L29/0653H01L29/6656H01L29/66545H01L29/66795H01L29/66818H01L29/7848
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Quick Facts
Patent No.
US 10,388,756
App. No.
15/869,087
Granted
Aug 20, 2019
Kind
B2
Abstract

A method for fabricating a semiconductor device is disclosed. A fin is formed on a substrate. The fin protrudes from a trench isolation layer on a substrate. The fin comprises a source region, a drain region and a channel region therebetween. A dummy gate strides across the fin and surrounding the channel region. An upper portion of the fin is removed so as to form a hollow channel underneath the dummy gate. A replacement channel layer is in-situ epitaxially grown in the hollow channel.

Claims (25)

1. A semiconductor device, comprising:

a bulk semiconductor substrate;

a fin on the bulk semiconductor substrate, the fin comprising a source region, a drain region and a channel region therebetween;

a replacement channel layer disposed in the channel region;

a gate striding across the fin and surrounding the replacement channel layer;

an epitaxial source layer in the source region; and

an epitaxial drain layer in the drain region, wherein the epitaxial source layer and the epitaxial drain layer are contiguous with the replacement channel layer, and wherein a bottom surface of the epitaxial source layer and the epitaxial drain layer is shallower than a bottom surface of the replacement channel layer.

2. The semiconductor device according to claim 1 , wherein the replacement channel layer comprises a SiGe layer.

3. The semiconductor device according to claim 2 , wherein the SiGe layer is an un-doped SiGe layer.

4. The semiconductor device according to claim 1 , wherein the thickness of the replacement channel layer ranges between 400˜600 angstroms.

5. The semiconductor device according to claim 4 , wherein the thickness of the replacement channel layer is uniform between the source region and the drain region.

6. The semiconductor device according to claim 1 , wherein the semiconductor device is a PMOS finFET device, and wherein the epitaxial source layer and the epitaxial drain layer are boron-doped SiGe epitaxial layers.

7. The semiconductor device according to claim 1 further comprising a gate dielectric layer between the gate and the replacement channel layer, and wherein the gate dielectric layer is in direct contact with the replacement channel layer.

8. A semiconductor device, comprising:

a bulk semiconductor substrate;

a fin on the bulk semiconductor substrate, the fin comprising a source region, a drain region and a channel region therebetween;

a replacement channel layer disposed in the channel region, wherein the replacement channel layer has a tapered sectional profile between the source region and the drain region;

a gate striding across the fin and surrounding the replacement channel layer;

an epitaxial source layer in the source region; and

an epitaxial drain layer in the drain region.

9. The semiconductor device according to claim 8 , wherein the fin comprises an upwardly convex surface that is in direct contact with a bottom surface of the replacement channel layer.

10. The semiconductor device according to claim 8 , wherein the replacement channel layer comprises a SiGe layer.

11. The semiconductor device according to claim 10 , wherein the SiGe layer is an un-doped SiGe layer.

12. The semiconductor device according to claim 8 , wherein the semiconductor device is a PMOS finFET device, and wherein the epitaxial source layer and the epitaxial drain layer are boron-doped SiGe epitaxial layers.

13. The semiconductor device according to claim 8 further comprising a gate dielectric layer between the gate and the replacement channel layer, and wherein the gate dielectric layer is in direct contact with the replacement channel layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 12, 2018
From: CHEN, YEN-HSING; CHEN, CHUN-YU; HUANG, CHUNG-TING; HUANG, ZIH-HSUAN; SUNG, YU-CHIEN
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 044604/0611 →
Continuity (1)
Related Publication 20190221655A1 · Jul 18, 2019