IP Library Granted Patent US 10,438,899
Granted Patent B2
US 10,438,899 · App. 15/869,517 · Granted Oct 8, 2019

Semiconductor packages

Inventors: Young-lyong Kim (Anyang-si, KR); Hyun-soo Chung (Hwaseong-si, KR); Dong-hyeon Jang (Yongin-si, KR)
Assignee: Samsung Electronics Co., Ltd.
H01L23/552H01L23/345H01L23/367H01L23/4334H01L23/5384H01L24/10H01L24/19H01L24/20H01L24/13H01L24/16H01L24/17H01L24/29H01L24/32H01L24/48H01L24/73H01L24/83H01L24/92H01L24/97H01L25/0657H01L25/105H01L2224/12105H01L2224/13025H01L2224/16146H01L2224/16227H01L2224/17181H01L2224/2919H01L2224/2929H01L2224/29339H01L2224/29344H01L2224/29347H01L2224/29355H01L2224/32145H01L2224/32245H01L2224/48227H01L2224/73204H01L2224/73267H01L2224/83851H01L2224/83862H01L2224/83874H01L2224/92244H01L2224/97H01L2225/06513H01L2225/06517H01L2225/06541H01L2225/06565H01L2225/1035H01L2225/1058H01L2225/1094H01L2924/1431H01L2924/1434H01L2924/15311H01L2924/3025H01L2924/3511
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Quick Facts
Patent No.
US 10,438,899
App. No.
15/869,517
Granted
Oct 8, 2019
Kind
B2
Abstract

A semiconductor package including a heat spreading layer having at least one hole, a first semiconductor chip below the heat spreading layer, a redistribution structure below the first semiconductor chip, a first mold layer between the heat spreading layer and the redistribution structure, a shielding wall extending from the redistribution structure and the heat spreading layer and surrounding the first semiconductor chip, and a first conductive pillar extending from the redistribution structure into the hole may be provided.

Claims (57)

1. A semiconductor package comprising:

a heat spreading layer including at least one hole;

a first semiconductor chip below the heat spreading layer;

a redistribution structure below the first semiconductor chip;

a first mold layer between the heat spreading layer and the redistribution structure, the first mold layer filling the at least one hole;

a shielding wall extending from the redistribution structure to the heat spreading layer and surrounding the first semiconductor chip; and

a first conductive pillar extending from the redistribution structure into the at least one hole, the first conductive pillar and the heat spreading layer being spaced from each other by the first mold layer therebetween.

2. The semiconductor package according to claim 1 , wherein a height of the first conductive pillar is greater than a height of the shielding wall.

3. The semiconductor package according to claim 1 , wherein an upper surface of the first mold layer is coplanar with an upper surface of the heat spreading layer.

4. The semiconductor package according to claim 1 , wherein an upper surface of the first conductive pillar is coplanar with an upper surface of the heat spreading layer.

5. The semiconductor package according to claim 1 , wherein the heat spreading layer covers the first mold layer except for a portion of the first mold layer filling the at least one hole.

6. The semiconductor package according to claim 1 , further comprising:

a second conductive pillar extending from the redistribution structure to the first semiconductor chip.

7. The semiconductor package according to claim 6 , wherein a lower surface of the shielding wall, a lower surface of the first conductive pillar, and a lower surface of the second conductive pillar are coplanar.

8. The semiconductor package according to claim 1 , further comprising:

a chip adhesion layer between the heat spreading layer and the first semiconductor chip.

9. The semiconductor package according to claim 8 , further comprising:

a third conductive pillar extending from the heat spreading layer toward the first semiconductor chip.

10. A semiconductor package comprising:

a heat spreading layer including at least one chip portion, a shielding portion surrounding the at least one chip portion, and a hole portion outside the shielding portion and including at least one hole;

at least one first semiconductor chip below the at least one chip portion of the heat spreading layer;

at least one shielding wall in contact with and below the shielding portion of the heat spreading layer;

a first conductive pillar passing through the at least one hole included in the hole portion of the heat spreading layer;

a second conductive pillar below the at least one first semiconductor chip;

a first mold layer covering a sidewall of the at least one shielding wall, a sidewall of the first conductive pillar, a sidewall of the second conductive pillar, and a sidewall of the at least one first semiconductor chip; and

a redistribution structure below the first semiconductor chip and in contact with the at least one shielding wall, the first conductive pillar, and the second conductive pillar.

11. The semiconductor package according to claim 10 , further comprising:

a chip adhesion layer between the at least one chip portion of the heat spreading layer and the at least one first semiconductor chip.

12. The semiconductor package according to claim 10 , further comprising:

a third conductive pillar between the at least one chip portion of the heat spreading layer and the at least one first semiconductor chip; and

a chip adhesion layer filling a gap between the at least one chip portion of the heat spreading layer and the at least one first semiconductor chip.

13. The semiconductor package according to claim 10 , wherein

a diameter of the at least one hole is greater than a diameter of the first conductive pillar, and

the first mold layer fills a gap between an outer sidewall of the first conductive pillar and an inner sidewall of the at least one hole.

14. The semiconductor package according to claim 10 , wherein

the at least one chip portion of the heat spreading layer includes a plurality of laterally spaced chip portions,

the at least one first semiconductor chip includes a plurality of first semiconductor chips,

the at least one shielding wall includes a plurality of shielding walls,

the plurality of first semiconductor chips are disposed below the plurality of laterally spaced chip portions of the heat spreading layer, respectively, and

the plurality of first semiconductor chips are surrounded by the plurality of shielding walls, respectively.

15. The semiconductor package according to claim 10 , further comprising:

a second semiconductor chip below the chip portion of the heat spreading layer,

wherein the at least one shielding wall surrounds the second semiconductor chip.

16. A semiconductor package comprising:

a first semiconductor package;

a second semiconductor package on the first semiconductor package; and

an inter-package connection between the first semiconductor package and the second semiconductor package,

wherein the first semiconductor package comprises,

a redistribution structure,

a first semiconductor chip on the redistribution structure,

a heat spreading layer on the first semiconductor chip and including at least one hole,

a first mold layer between the heat spreading layer and the redistribution structure and covering a sidewall of the first semiconductor chip,

a shielding wall extending from the redistribution structure and the heat spreading layer and surrounding the first semiconductor chip, and

a first conductive pillar extending from the redistribution structure into the at least one hole, and

wherein the inter-package connection is spaced from the heat spreading layer.

17. The semiconductor package according to claim 16 , wherein the inter-package connection contacts the first conductive pillar.

18. The semiconductor package according to claim 16 , wherein a sum of a plane area of the heat spreading layer and a plane area of the at least one hole is substantially equal to a plane area of the redistribution structure.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE 1ST INVENTOR FIRST NAME WAS MISSPELLED PREVIOUSLY RECORDED ON REEL 044611 FRAME 0901. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 13, 2019
From: KIM, YOUNG-LYONG; CHUNG, HYUN-SOO; JANG, DONG-HYEON
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 050373/0767 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 12, 2018
From: KIM, YOUNG-IYONG; CHUNG, HYUN-SOO; JANG, DONG-HYEON
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 044611/0901 →
Priority Claims (1)
KR 10-2017-0100440 · Aug 8, 2017 · national
Continuity (1)
Related Publication 20190051612A1 · Feb 14, 2019
Cited By (2)
US 12,635,523 US 12,702,008