Optimized compute hardware for machine learning operations

1. A compute apparatus to perform machine learning operations, the compute apparatus comprising:

first circuitry to fetch a single instruction having multiple input operands, wherein the multiple input operands have an unequal bit-length, a first input operand having a first bit-length and a second input operand having a second bit-length;

second circuitry to decode the single instruction into a decoded instruction;

third circuitry to determine a smaller bit-length of the first bit-length and the second bit-length; and

a compute unit including hardware to perform a matrix operation on the multiple input operands to generate an output value having a bit length of the smaller bit length.

2. The compute apparatus as in claim 1 , wherein the single instruction is to cause the compute unit to perform an at least two-dimensional matrix multiply operation on the multiple input operands.

3. The compute apparatus as in claim 2 , wherein the single instruction is to cause the compute unit to perform at least one multiply-add operation.

4. The compute apparatus as in claim 2 , wherein the single instruction is to cause the compute unit to perform at least one multiply-accumulate operation.

5. The compute apparatus as in claim 2 , wherein the single instruction is to cause the compute unit to perform an at least two-dimensional matrix dot product operation.

6. The compute apparatus as in claim 1 , additionally including fourth circuitry to provide a precision configuration to the compute unit.

7. The compute apparatus as in claim 6 , the fourth circuitry to configure an operational precision of a functional unit within the compute unit.

8. The compute apparatus as in claim 1 , the compute unit to perform a matrix multiply operation on the multiple input operands, wherein the compute unit is to:

determine whether a multiply operation of the matrix multiply operation has a zero input; and

bypass the multiply operation having the zero input.

9. The compute apparatus as in claim 8 , wherein to bypass the multiply operation having the zero input, the compute unit is to bypass scheduling of the multiply operation having the zero input.

10. The compute apparatus as in claim 8 , wherein to bypass the multiply operation having the zero input, the compute unit is to

substitute a no-operation opcode for a multiply operation opcode for a functional unit associated with the zero input.

11. A data processing system comprising:

a memory device to store instructions for execution by one or more processors of the data processing system; and

a general-purpose graphics processing unit including:

first circuitry to decode a single instruction including multiple operands into a single decoded instruction, the multiple operands including multiple input operands having an unequal bit-length, the multiple input operands including a first input operand having a first bit-length and a second input operand having a second bit-length, wherein the general-purpose graphics processing unit is to generate an output value having a bit length of the smaller bit length;

second circuitry to determine a smaller bit-length of the first bit-length and the second bit-length; and

a compute unit including hardware to perform a matrix operation on the multiple operands to generate the output value having a bit-length equal to the smaller bit-length.

12. The data processing system as in claim 11 , wherein the single instruction is to cause the compute unit to perform an at least two-dimensional matrix multiply operation on the multiple operands.

13. The data processing system as in claim 11 , wherein the single instruction is to cause the compute unit to perform at least one multiply-add operation, an at least two-dimensional matrix dot product operation, or at least one multiply-accumulate operation.

14. A method on a general-purpose graphics processing unit (GPGPU), the method comprising:

fetching a single instruction having multiple input operands, wherein the multiple input operands have an unequal bit-length, a first input operand having a first bit-length and a second input operand having a second bit-length;

decoding the single instruction into a decoded instruction;

determining a smaller bit-length of the first bit-length and the second bit-length; and

performing, via a compute unit of the GPGPU, a matrix operation on the multiple input operands to generate an output value having a bit length of the smaller bit length.

15. The method as in claim 14 , wherein the single instruction is to cause the compute unit to perform an at least two-dimensional matrix multiply operation on the multiple input operands.

16. The method as in claim 15 , wherein the single instruction is to cause the compute unit to perform at least one multiply-add operation or multiply-accumulate operation.

17. The method as in claim 15 , wherein the single instruction is to cause the compute unit to perform an at least two-dimensional matrix dot product operation.

18. The method as in claim 14 , additionally including providing, via a circuit of the GPGPU, a precision configuration to the compute unit to configure an operational precision of a functional unit within the compute unit.

19. The method as in claim 14 , additionally including performing a matrix multiply operation on the multiple input operands via the compute unit of the GPGPU, wherein performing the matrix multiply operation includes:

determining whether a multiply operation of the matrix multiply operation has a zero input; and

bypassing the multiply operation having the zero input.

20. The method as in claim 19 , wherein bypassing the multiply operation having the zero input includes bypassing scheduling of the multiply operation having the zero input or substituting a no-operation opcode for a multiply operation opcode for a functional unit associated with the zero input.