Logic semiconductor device

1. A semiconductor device comprising:

a plurality of stacked transistors,

wherein:

each of the transistors comprises:

a semiconductor column including a first conductive region of a first conductivity type, a second conductive region of a second conductivity type, an intrinsic region disposed between the first conductive region and the second conductive region, and a barrier region of the first conductivity type disposed between the intrinsic region and the second conductive region;

a gate electrode disposed to cover the intrinsic region; and

a gate insulating layer disposed between the gate electrode and the intrinsic region;

wherein not all of the plurality of stacked transistors have a same first conductivity type, and

wherein:

the plurality of stacked transistors include a first transistor disposed at a lower portion and a second transistor disposed above the first transistor,

the first conductivity type of the first transistor is n-type, and

the first conductivity type of the second transistor is p-type.

2. The semiconductor device as set forth in claim 1 , wherein:

the semiconductor column of the first transistor includes the first conductive region, the intrinsic region, the barrier region, and the second conductive region which are sequentially disposed in a vertical direction, and

the semiconductor column of the second transistor includes the second conductive region, the barrier region, the intrinsic region, and the first conductive region which are sequentially disposed in the vertical direction.

3. The semiconductor device as set forth in claim 2 , wherein:

the gate electrode of the first transistor is electrically connected to the gate electrode of the second transistor to receive an input signal indicating logic “1” or “0”,

the second gate electrode of the first transistor is electrically connected to the second region of the second transistor to provide an output signal,

the first conductive region of the first transistor is grounded,

the first conductive region of the second transistor is connected to an applied voltage,

the first transistor and the second transistor provide a logic inverter, and

the input signal and the output signal are opposite in sign.

4. The semiconductor device as set forth in claim 3 , wherein:

the logic inverter retains an output signal of a previous state even when the input signal is removed from the gate electrode of the first transistor.

5. The semiconductor device as set forth in claim 1 , wherein:

the semiconductor column of the first transistor includes the second conductive region, the barrier region, the intrinsic region, and the first conductive region which are sequentially disposed in a vertical direction, and

the semiconductor column of the second transistor includes the second conductive region, the barrier region, the intrinsic region, and the first conductive region which are sequentially disposed in the vertical direction.

6. The semiconductor device as set forth in claim 1 , wherein:

the plurality of stacked transistors include a pair of first transistors disposed at a lower layer and a pair of second transistors disposed at an upper layer,

the semiconductor column of the first transistor includes the first conductive region, the intrinsic region, the barrier region, and the second conductive region which are sequentially disposed in a vertical direction,

the semiconductor column of the second transistor includes the second conductive region, the barrier region, the intrinsic region, and the first conductive region which are sequentially disposed in the vertical direction, and

the first transistor and the second transistor constitute a NOR logic circuit or a NAND logic circuit.

7. The semiconductor device as set forth in claim 1 , wherein:

the plurality of stacked transistors include a pair of first transistors disposed at a lower layer and a pair of second transistors disposed at an upper layer,

the semiconductor column of the first transistor includes the second conductive region, the barrier region, the intrinsic region, and the first conductive region which are sequentially disposed in a vertical direction,

the semiconductor column of the second transistor includes the second conductive region, the barrier region, the intrinsic region, and the first conductive region which are sequentially disposed in the vertical direction, and

the first transistor and the second transistor constitute a NOR logic circuit or a NAND logic circuit.

8. The semiconductor device as set forth in claim 1 , wherein:

the first transistor includes:

a first lower interlayer dielectric disposed on a substrate;

a second lower interlayer dielectric disposed on the first lower interlayer dielectric;

a lower gate electrode disposed between the first lower interlayer dielectric and the second lower interlayer dielectric;

a lower semiconductor column disposed through the second lower interlayer dielectric, the lower gate electrode, and the first lower interlayer dielectric;

a lower gate insulating layer disposed between the lower semiconductor column and the lower gate electrode;

a lower interconnection disposed on the second lower interlayer dielectric and the lower semiconductor column; and

a third lower interlayer dielectric disposed on the lower interconnection.

9. The semiconductor device as set forth in claim 8 , wherein:

the second transistor includes:

a first upper interlayer dielectric disposed on the third lower interlayer dielectric;

a second upper interlayer dielectric disposed on the first upper interlayer dielectric;

an upper gate electrode disposed between the first upper interlayer dielectric and the second upper interlayer dielectric;

an upper semiconductor column disposed through the second upper interlayer dielectric, the upper gate electrode, and the first upper interlayer dielectric;

an upper gate insulating layer disposed between the upper semiconductor column and the upper gate electrode; and

an upper interconnection disposed between the second upper interlayer dielectric and the upper semiconductor column.

10. The semiconductor device as set forth in claim 1 , wherein:

the first transistor includes:

a first lower interlayer dielectric disposed on a substrate;

a second lower interlayer dielectric disposed on the first lower interlayer dielectric;

the gate electrode disposed between the first lower interlayer dielectric and the second lower interlayer dielectric;

the semiconductor column disposed through the second lower interlayer dielectric, the gate electrode, and the first lower interlayer dielectric;

the gate insulating layer disposed between the semiconductor column and the gate electrode;

a lower interconnection disposed on the second lower interlayer dielectric and the semiconductor column; and

a third lower interlayer dielectric disposed on the lower interconnection, and further comprising:

a gate isolation layer isolating the gate electrode;

a lower auxiliary interconnection extending in contact with a bottom surface of the semiconductor column; and

a lower interconnection contact plug connected to the lower auxiliary interconnection through the gate isolation layer.

11. The semiconductor device as set forth in claim 9 , further comprising:

an upper gate isolation layer isolating the upper gate electrode;

an upper auxiliary interconnection extending in contact with a bottom surface of the upper semiconductor column; and

an upper interconnection contact plug connected to the upper auxiliary interconnection through the upper gate isolation layer.

12. A semiconductor device comprising:

a plurality of stacked transistors,

wherein:

the plurality of stacked transistors comprise:

a semiconductor column including a first conductive region of first conductivity type, a second conductive region of second conductivity type, an intrinsic region disposed between the first conductive region and the second conductive region, and a barrier region of the first conductivity type disposed between the intrinsic region and the second conductive region;

a gate electrode disposed to cover the intrinsic region; and

a gate insulating layer disposed between the gate electrode and the intrinsic region,

wherein not all of the plurality of stacked transistors have a same first conductive type,

wherein:

the plurality of stacked transistors include a pair of first transistors disposed at a lower layer and a pair of second transistors disposed at an upper layer, and

the first transistor and the second transistor constitute a NOR logic circuit or a NAND logic circuit.

13. The semiconductor device as set forth in claim 12 , wherein:

an input signal applied to the gate electrode of the transistor is a positive first gate voltage indicating a first logic state and a negative second gate voltage indicating a second logic state, and

the NOR logic circuit or the NAND logic circuit outputs data of a previous state even when the input signal is removed.

14. A semiconductor device comprising:

a plurality of stacked transistors,

wherein:

each of the transistors comprises:

a semiconductor column including a first conductive region of a first conductivity type, a second conductive region of a second conductivity type, an intrinsic region disposed between the first conductive region and the second conductive region, and a barrier region of the first conductivity type disposed between the intrinsic region and the second conductive region;

a gate electrode disposed to cover the intrinsic region; and

a gate insulating layer disposed between the gate electrode and the intrinsic region,

wherein not all of the plurality of stacked transistors have a same first conductive type,

wherein:

the plurality of stacked transistors include an n-channel semiconductor device in which the first conductivity type of the semiconductor column is n-type and a p-channel semiconductor device in which the first conductivity type of the semiconductor column is p-type, respectively, and

the plurality of stacked transistors is configured to perform at least one of inverter, NAND, and NOR logic operations.

15. The semiconductor device as set forth in claim 14 , wherein:

the p-channel semiconductor device and the n-channel semiconductor device have a stacked structure.