Apparatus for radio-frequency receiver with in-phase/quadrature calibration and associated methods
An apparatus includes a radio-frequency (RF) receiver. The RF receiver includes an analog-to-digital converter (ADC) to convert an analog input signal to a digital output signal in response to an ADC clock signal. The RF receiver further includes a frequency generator to selectively provide either a clock signal to be provided as the ADC clock signal or a signal to be used for in-phase-quadrature (IQ) calibration of the RF receiver.
1. An apparatus, comprising:
a radio-frequency (RF) receiver, comprising:
an analog-to-digital converter (ADC) to convert an analog input signal to a digital output signal in response to an ADC clock signal; and
a frequency generator comprising a single phase locked loop (PLL) to selectively provide either a clock signal to be provided as the ADC clock signal or a signal to be used for in-phase-quadrature (IQ) calibration of the RF receiver.
2. The apparatus according to claim 1 , wherein the ADC comprises a delta sigma ADC.
3. The apparatus according to claim 1 , wherein the clock signal is provided to a first input of a multiplexer (MUX), and wherein an output of the MUX provides the ADC clock signal to the ADC.
4. The apparatus according to claim 1 , wherein the signal to be used for IQ calibration of the RF receiver is provided to a low noise amplifier (LNA).
5. The apparatus according to claim 3 , wherein a signal derived from an output of a frequency synthesizer in the RF receiver is provided to a second input of the MUX.
6. The apparatus according to claim 5 , wherein in response to a select signal the MUX provides either the signal derived from the output of the frequency synthesizer or the clock signal to the ADC as the ADC clock signal.
7. The apparatus according to claim 5 , further comprising a divider coupled to receive an output signal of the frequency synthesizer and provide the signal derived from the output of the frequency synthesizer by dividing a frequency of the output of the frequency synthesizer.
8. The apparatus according to claim 5 , wherein a value of the select signal depends on whether the RF receiver operates in a receive mode of operation or in an IQ calibration mode of operation.
9. The apparatus according to claim 6 , further comprising a controller to cause the frequency generator to selectively provide either the clock signal or the signal to be used for IQ calibration of the RF receiver by providing the select signal to the MUX.
10. An apparatus, comprising:
a radio-frequency (RF) receiver having a receive mode of operation and an in-phase-quadrature (IQ) calibration mode of operation, the RF receiver comprising:
an analog-to-digital converter (ADC) to convert an analog input signal to a digital output signal; and
a single phase locked loop (PLL) to provide either a clock signal to clock the ADC in the receive mode of operation or a signal to be used for in-phase-quadrature (IQ) calibration mode of operation.
11. The apparatus according to claim 10 , wherein the RF receiver selectively operates in the receive mode of operation or in the IQ calibration mode of operation.
12. The apparatus according to claim 10 , further comprising a multiplexer (MUX) having a first input coupled to receive a signal derived from an output signal of a frequency synthesizer and a second input coupled to receive the clock signal, the MUX further having an output coupled to provide a signal to clock the ADC.
13. The apparatus according to claim 12 , further comprising a controller to control whether the RF receiver operates in the receive mode of operation or in the IQ calibration mode of operation by providing a select signal to the MUX.
14. The apparatus according to claim 13 , wherein in the receive mode of operation the controller causes the MUX to provide the clock signal to clock the ADC, and wherein in the IQ calibration mode of operation, the controller causes the MUX to provide the signal derived from the output signal of the frequency synthesizer to clock the ADC.
15. A method of operating a radio-frequency (RF) receiver, the method comprising using a single phase locked loop (PLL) in a frequency generator to selectively provide either a clock signal for an analog-to-digital converter (ADC) to convert an analog input signal to a digital output signal, or a signal to be used for in-phase-quadrature (IQ) calibration of the RF receiver.
16. The method according to claim 15 , wherein the ADC comprises a delta sigma ADC.
17. The method according to claim 15 , further comprising using a multiplexer (MUX) to selectively provide the clock signal for the ADC.
18. The method according to claim 15 , wherein the frequency generator provides the clock signal for the ADC in a receive mode of operation of the RF receiver, and wherein the frequency generator provides the signal to be used for IQ calibration of the RF receiver in an IQ calibration mode of operation of the RF receiver.
19. The method according to claim 17 , wherein using the MUX to selectively provide the clock signal for the ADC comprises selectively providing either the clock signal from the single PLL or a signal derived from an output signal of a frequency synthesizer.
20. The method according to claim 19 , further comprising using as a local oscillator (LO) signal derived from the output signal of the frequency synthesizer.