IP Library Granted Patent US 12,544,006
Granted Patent B2
US 12,544,006 · App. 15/876,030 · Granted Feb 10, 2026

System and method for simultaneous stimulation and recording using system-on-chip (SoC) architecture

Inventors: Zhi Yang (Minneapolis, MN); Jian Xu (Minneapolis, MN); Anh Tuan Nguyen (Minneapolis, MN); Tong Wu (Minneapolis, MN)
Assignee: REGENTS OF THE UNIVERSITY OF MINNESOTA
A61B5/4836A61B5/24A61B5/4064A61B5/685A61B5/686A61B5/7203A61B5/7217A61B5/7225A61B5/4041A61B2505/09A61B2562/028A61B2562/043A61B2562/046A61B2562/166
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Quick Facts
Patent No.
US 12,544,006
App. No.
15/876,030
Granted
Feb 10, 2026
Kind
B2
Abstract

An implantable neuromodulation system is provided comprising at least one stimulation microelectrode, at least one microelectrode, and a frequency-shaping amplifier (FSA). The at least one stimulation microelectrode is configured to deliver a desired electrical stimulation to a neuronal population. The at least one recording microelectrode is configured to receive neural signals from the neuronal population. The FSA is coupled to the at least one recording microelectrode. The FSA is configured to allow for simultaneous electrical recording and electrical stimulation of the neuronal population.

Claims (34)

1 . An implantable neuromodulation system comprising:

a microelectrode array including a stimulation microelectrode to deliver a desired electrical stimulation to a neuronal population and a recording microelectrode to receive neural signals from the neuronal population; and

a frequency-shaping amplifier (FSA) circuit including an FSA, the FSA circuit coupled to the microelectrode array, wherein the FSA circuit implements at least one of a multi-phase data sampling and processing technique, a modified parasitic capacitor suppression method, or a modified auto-zero (kT/C) noise cancellation scheme to improve signal-to-noise ratio of signals received by the FSA circuit;

wherein the FSA circuit comprises a feedback gain boosting path connected between an output terminal of the FSA and an inverting input terminal of the FSA, the feedback gain boosting path configured to reduce noise at low frequencies by transferring charge on a first capacitor of the FSA circuit to a second capacitor of the FSA circuit,

wherein the FSA circuit is configured to receive and electrically record neural signals received by the recording microelectrode of the microelectrode array from the neuronal population simultaneously with delivering electrical stimulation to the neuronal population using the stimulation microelectrode of the microelectrode array, and

wherein the stimulation microelectrode and the recording microelectrode are separated by between tens to hundreds of micrometers.

2 . The system of claim 1 , wherein the FSA circuit is configured to amplify, filter, and digitize the neural signals while suppressing stimulation artifacts.

3 . The system of claim 1 , wherein the microelectrode array is implemented on a single silicon chip in a high-voltage complementary metal-oxide-semiconductor (CMOS) process.

4 . The system of claim 1 , wherein the FSA circuit includes multi-phase data sampling and processing circuits that implement the multi-phase data sampling and processing technique, modified parasitic capacitor suppression method circuits that implement the modified parasitic capacitor suppression method, and modified auto-zero noise cancellation scheme circuits that implement the modified auto-zero (kT/C) noise cancellation scheme to improve the signal-to-noise ratio of signals output from the FSA circuit relative to signals received by the FSA circuit.

5 . The system of claim 4 , wherein the multi-phase data sampling and processing circuits are configured to boost a closed-loop gain of the implantable neuromodulation system without decreasing sampling frequency or input impedance.

6 . The system of claim 4 , wherein the modified parasitic capacitor suppression method circuits are configured to block charge transfer from amplifier input parasitic capacitors.

7 . The system of claim 4 , wherein the modified auto-zero noise cancellation scheme is configured to allow removal of noise appearing on a feedback capacitor from a switch-on resistor.

8 . The system of claim 1 , wherein the system is configured as a system-on-chip.

9 . The system of claim 8 , wherein the system-on-chip includes a recorder circuit block, a stimulation circuit block, and a digital circuit block that are physically isolated from each other, and that each operate on corresponding voltage rails having differing voltages.

10 . The system of claim 8 , wherein the system-on-chip is incorporated in an implantable medical device.

11 . An implantable neuromodulation system comprising:

a microelectrode array including a stimulation microelectrode and a recording microelectrode, wherein a spacing between the stimulation microelectrode and the recording microelectrode is between tens to hundreds of micrometers, the stimulation microelectrode is configured to deliver a desired electrical stimulation to a neuronal population, and the recording microelectrode is configured to receive neural signals from the neuronal population; and

a frequency-shaping amplifier (FSA) circuit including an FSA, the FSA circuit coupled to the microelectrode array;

wherein the FSA circuit comprises a feedback gain boosting path connected between an output terminal of the FSA and an input terminal of the FSA, the feedback gain boosting path configured to transfer charge on a first capacitor of the FSA circuit to a second capacitor of the FSA circuit,

wherein the system is configured as a system-on-chip, and

wherein the FSA circuit is configured to perform electrical recording of the neural signals received by the recording microelectrode from the neuronal population during delivery of the desired electrical stimulation to the neuronal population by the stimulation microelectrode.

12 . The system of claim 11 , further comprising a recorder circuit block, a stimulation circuit block, and a digital circuit block that are physically isolated from each other, and that each operate on corresponding voltage rails having differing voltages.

13 . The system of claim 11 , further comprising a housing incorporating the system-on-chip to form an implantable medical device.

14 . An implantable neuromodulation system comprising:

a microelectrode array including a stimulation microelectrode to deliver a desired electrical stimulation to a neuronal population and a recording microelectrode to receive neural signals from the neuronal population; and

a frequency-shaping amplifier (FSA) circuit including an FSA, the FSA circuit coupled to the microelectrode array to improve a signal-to-noise ratio of the neural signals received from the neuronal population via the recording microelectrode;

wherein the FSA circuit comprises a feedback gain boosting path connected between an output terminal of the FSA and an input terminal of the FSA, the feedback gain boosting path configured to transfer charge on a first capacitor of the FSA circuit to a second capacitor of the FSA circuit,

wherein the FSA circuit is configured to receive and electrically record neural signals received by the recording microelectrode of the microelectrode array from the neuronal population simultaneously with delivering electrical stimulation to the neuronal population using the stimulation microelectrode of the microelectrode array, and

wherein the stimulation microelectrode and the recording microelectrode are separated by between tens to hundreds of micrometers in the microelectrode array.

15 . The system of claim 14 , wherein the input terminal of the FSA comprises an inverting input terminal of the FSA.

16 . The system of claim 15 , wherein:

the feedback gain boosting path is configured to transfer the charge on the first capacitor to the second capacitor during a second time period that occurs after a first time period; and

the feedback gain boosting path is not configured to transfer the charge on the first capacitor to the second capacitor during the first time period.

17 . The system of claim 16 , wherein the feedback gain boosting path is configured to transfer the charge on the first capacitor to the second capacitor in accordance with a ratio of a capacitance of the first capacitor to a capacitance of the second capacitor.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 4, 2022
From: YANG, ZHI; XU, JIAN; NGUYEN, ANH TUAN
To: REGENTS OF THE UNIVERSITY OF MINNESOTA
Reel/Frame 059493/0731 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 4, 2020
From: WU, TONG
To: REGENTS OF THE UNIVERSITY OF MINNESOTA
Reel/Frame 052834/0020 →
Continuity (2)
Provisional Application 62448286 · Jan 19, 2017
Related Publication 20180199841A1 · Jul 19, 2018
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